18.6.6 Auxiliary PLL Control
Note: The system unlock
sequence must be done before this register can be
written.
| Name: | APLLCON |
| Offset: | 0x14 |
| Reset: | 0xC0010028 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EPLLPOSTDIV2[5:0] | |||||||||
| Access | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | |||
Bits 5:0 – EPLLPOSTDIV2[5:0] EPLL Post Divider
| Value | Description |
|---|---|
| 1 ≤ xPLLPOSTDIV2 ≤ 63 | Divide by xPLLPOSTDIV2 |
| 0 | Not used |