18.6.3 SPLL Control
Note: Perform the system
unlock sequence before this register is
written.
| Name: | SPLLCON |
| Offset: | 0x8 |
| Reset: | 0xC0010028 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SPLL_BYP[1:0] | |||||||||
| Access | R/W/L | R/W/L | |||||||
| Reset | 1 | 1 | |||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SPLL2POSTDIV2[3:0] | |||||||||
| Access | R/W/L | R/W/L | R/W/L | R/W/L | |||||
| Reset | 0 | 0 | 0 | 1 | |||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SPLL1POSTDIV1[7:0] | |||||||||
| Access | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | R/W/L | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SPLLFLOCK | SPLLPWDN | ||||||||
| Access | R/W/L | R/W/L | |||||||
| Reset | 0 | 1 |
Bits 31:30 – SPLL_BYP[1:0] SPLL Bypass; SPLL_CLK2 clock source selection
Note:
- Dictates the clock source for ADC CP (Analog-to-Digital Converter Charge Pump) (SPLL_CLK2) Clock generation only
- Preselect the clock sources and keep them ready before the need of ADC CP arrives. Failure to do so results in loss of clock for one or two cycles when ADC CP is enabled.
| Value | Description |
|---|---|
| 00 | RFPLL Clock is the clock source for ADC CP Clock Generation. |
| x1 | FRC is used as clock source for ADC CP Clock Generation. |
| 10 | POSC is used as clock source for ADC CP Clock Generation. |
Bits 19:16 – SPLL2POSTDIV2[3:0] ADC-CP (SPLL2) Post Divide Value
| Value | Description |
|---|---|
| 1 ≤ SPLLPOSTDIV2 ≤ 15 | Divide by SPLL2POSTDIV2 |
| 0 | No Clock; Clock disabled |
Bits 15:8 – SPLL1POSTDIV1[7:0] SPLL1 Post Divide Value
| Value | Description |
|---|---|
| 2 ≤ SPLLPOSTDIV ≤ 255 | Divide by SPLL1POSTDIV1 |
| 0,1 | Divide by 1 |
Bit 4 – SPLLFLOCK System PLL Force Lock
| Value | Description |
|---|---|
| 1 | Force the SPLL lock signal to be asserted |
| 0 | Do not force the SPLL lock signal to be asserted |
Bit 3 – SPLLPWDN PLL Power Down Register bit
| Value | Description |
|---|---|
| 1 | PLL is powered down |
| 0 | PLL is active |