18.6.8 Software Reset Register
Note: The system unlock sequence must be
done before writing this register. For more details, see Register Locking
from Related Links.
| Name: | RSWRST |
| Offset: | 0x1C |
| Reset: | 0x00000000 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SWRST | |||||||||
| Access | W/HC | ||||||||
| Reset | 0 |
Bit 0 – SWRST Software Reset Trigger bit
‘1’ = Enable SWR event. A subsequent read of this register
triggers the system Reset sequence. The system unlock sequence must be done
before the bit can be written. This bit always reads a value of logic
‘0’.