2.3.4.1.1 Timing Characteristics

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Table 2-39. 3.3V LVTTL / 3.3V LVCMOS High Slew Worst Military-Case Conditions: T_J = 125 °C, Worst-Case VCC = 1.425V, Worst-Case VCCxxxxIOBx = 3.0V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Drive  Strength	Speed Grade	t_DOUT	t_DP	t_DIN	t_PY	t_EOUT	t_ZL	t_ZH	t_LZ	t_HZ	t_ZLS	t_ZHS	Units
4 mA	Std.	0.62	7.71	0.04	1.04	0.41	7.85	6.61	2.70	2.64	10.06	8.82	ns
4 mA	–1	0.52	6.43	0.03	0.86	0.34	6.55	5.51	2.25	2.20	8.38	7.35	ns
8 mA	Std.	0.62	4.97	0.04	1.04	0.41	5.06	4.11	3.05	3.24	7.27	6.31	ns
8 mA	–1	0.52	4.14	0.03	0.86	0.34	4.22	3.42	2.54	2.70	6.05	5.26	ns
12 mA¹	Std.	0.62	3.61	0.04	1.04	0.41	3.68	2.86	3.28	3.63	5.88	5.07	ns
12 mA¹	–1	0.52	3.01	0.03	0.86	0.34	3.06	2.39	2.74	3.02	4.90	4.22	ns
16 mA	Std.	0.62	3.41	0.04	1.04	0.41	3.47	2.60	3.33	3.72	5.67	4.81	ns
16 mA	–1	0.52	2.84	0.03	0.86	0.34	2.89	2.17	2.78	3.10	4.73	4.01	ns
24 mA	Std.	0.62	3.14	0.04	1.04	0.41	3.20	2.17	3.39	4.10	5.40	4.38	ns
24 mA	–1	0.52	2.62	0.03	0.86	0.34	2.67	1.81	2.83	3.41	4.50	3.65	ns

Note:

Denotes the software default selection. This note is applicable for the entire row.
For specific junction temperature and voltage supply levels, refer to Table 2-7 for derating values.

Table 2-40. 3.3V LVTTL/3.3V LVCMOS Low Slew Worst Military-Case Conditions: TJ = 125 °C, Worst-Case VCC = 1.425V, Worst-Case VCCxxxxIOBx = 3.0V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Drive Strength	Speed Grade	t_DOUT	t_DP	t_DIN	t_PY	t_EOUT	t_ZL	t_ZH	t_LZ	t_HZ	t_ZLS	t_ZHS	Units
4 mA	Std.	0.62	10.44	0.04	1.04	0.41	10.63	8.80	2.70	2.48	12.83	11.01	ns
4 mA	–1	0.52	8.70	0.03	0.86	0.34	8.86	7.34	2.25	2.07	10.70	9.17	ns
8 mA	Std.	0.62	7.45	0.04	1.04	0.41	7.59	6.27	3.04	3.08	9.79	8.47	ns
8 mA	–1	0.52	6.21	0.03	0.86	0.34	6.32	5.22	2.54	2.56	8.16	7.06	ns
12 mA	Std.	0.62	5.73	0.04	1.04	0.41	5.84	4.90	3.28	3.46	8.04	7.11	ns
12 mA	–1	0.52	4.78	0.03	0.86	0.34	4.87	4.09	2.73	2.88	6.70	5.92	ns
16 mA	Std.	0.62	5.36	0.04	1.04	0.41	5.46	4.60	3.33	3.56	7.67	6.81	ns
16 mA	–1	0.52	4.47	0.03	0.86	0.34	4.55	3.83	2.77	2.97	6.39	5.67	ns
24 mA	Std.	0.62	5.00	0.04	1.04	0.41	5.09	4.58	3.39	3.92	7.29	6.79	ns
24 mA	–1	0.52	4.16	0.03	0.86	0.34	4.24	3.82	2.82	3.27	6.08	5.66	ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 for derating values.

Table 2-41. 3.3V LVTTL / 3.3V LVCMOS High Slew Worst Military-Case Conditions: T_J = 125 °C, Worst-Case VCC = 1.425V, Worst-Case VCCxxxxIOBx = 3.0V Applicable to MSS I/O Banks
Drive  Strength	Speed Grade	t_DOUT	t_DP	t_DIN	t_PY	t_PYS	t_EOUT	t_ZL	t_ZH	t_LZ	t_HZ	Units
8 mA₁	Std.	0.23	2.47	0.09	1.00	1.40	0.23	2.52	1.99	2.35	2.62	ns
8 mA₁	–1	0.19	2.06	0.08	0.84	1.16	0.19	2.10	1.66	1.96	2.19	ns

Note:

Denotes the software default selection. This note is applicable for the entire row.
For specific junction temperature and voltage supply levels, refer to Table 2-7 for derating values.

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