2.3.4.3.1 Timing Characteristics

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Table 2-51. 1.8V LVCMOS High Slew Worst Military-Case Conditions: T_J = 125 °C, Worst-Case VCC = 1.425V, Worst-Case VCCxxxxIOBx = 1.7V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Drive Strength	Speed Grade	t_DOUT	t_DP	t_DIN	t_PY	t_EOUT	t_ZL	t_ZH	t_LZ	t_HZ	t_ZLS	t_ZHS	Units
2 mA	Std.	0.62	11.85	0.04	1.22	0.41	9.22	11.85	2.80	1.70	11.42	14.05	ns
2 mA	–1	0.52	9.87	0.03	1.02	0.34	7.68	9.87	2.33	1.42	9.52	11.71	ns
4 mA	Std.	0.62	6.91	0.04	1.22	0.41	5.92	6.91	3.26	2.85	8.13	9.12	ns
4 mA	–1	0.52	5.76	0.03	1.02	0.34	4.94	5.76	2.72	2.38	6.77	7.60	ns
6 mA	Std.	0.62	4.46	0.04	1.22	0.41	4.27	4.46	3.58	3.40	6.48	6.66	ns
6 mA	–1	0.52	3.71	0.03	1.02	0.34	3.56	3.71	2.98	2.84	5.40	5.55	ns
8 mA	Std.	0.62	3.95	0.04	1.22	0.41	4.02	3.93	3.65	3.55	6.23	6.14	ns
8 mA	–1	0.52	3.29	0.03	1.02	0.34	3.35	3.28	3.04	2.96	5.19	5.12	ns
12 mA¹	Std.	0.62	3.62	0.04	1.22	0.41	3.68	3.06	3.75	4.09	5.89	5.26	ns
12 mA¹	–1	0.52	3.01	0.03	1.02	0.34	3.07	2.55	3.12	3.41	4.91	4.39	ns
16 mA	Std.	0.62	3.62	0.04	1.22	0.41	3.68	3.06	3.75	4.09	5.89	5.26	ns
16 mA	–1	0.52	3.01	0.03	1.02	0.34	3.07	2.55	3.12	3.41	4.91	4.39	ns

Note:

Denotes the software default selection. This note is applicable for the entire row.
For specific junction temperature and voltage supply levels, refer to Table 2-7 for derating values.

Table 2-52. 1.8V LVCMOS Low Slew Worst Military-Case Conditions: T_J = 125 °C, Worst-Case VCC = 1.425V, Worst-Case VCCxxxxIOBx = 1.7V Applicable to FPGA I/O Banks, I/O Assigned to EMC I/O Pins
Drive Strength	Speed Grade	t_DOUT	t_DP	t_DIN	t_PY	t_EOUT	t_ZL	t_ZH	t_LZ	t_HZ	t_ZLS	t_ZHS	Units
2 mA	Std.	0.62	15.25	0.04	1.22	0.41	14.43	15.25	2.80	1.65	16.63	17.46	ns
2 mA	–1	0.52	12.71	0.03	1.02	0.34	12.02	12.71	2.34	1.37	13.86	14.55	ns
4 mA	Std.	0.62	10.43	0.04	1.22	0.41	10.62	10.31	3.27	2.75	12.82	12.51	ns
4 mA	–1	0.52	8.69	0.03	1.02	0.34	8.85	8.59	2.72	2.29	10.69	10.42	ns
6 mA	Std.	0.62	8.21	0.04	1.22	0.41	8.36	7.75	3.58	3.30	10.57	9.96	ns
6 mA	–1	0.52	6.84	0.03	1.02	0.34	6.97	6.46	2.98	2.75	8.81	8.30	ns
8 mA	Std.	0.62	7.66	0.04	1.22	0.41	7.80	7.22	3.65	3.44	10.01	9.43	ns
8 mA	–1	0.52	6.38	0.03	1.02	0.34	6.50	6.02	3.04	2.87	8.34	7.86	ns
12 mA	Std.	0.62	7.24	0.04	1.22	0.41	7.38	7.23	3.75	3.96	9.58	9.43	ns
12 mA	–1	0.52	6.04	0.03	1.02	0.34	6.15	6.02	3.13	3.30	7.98	7.86	ns
16 mA	Std.	0.62	7.24	0.04	1.22	0.41	7.38	7.23	3.75	3.96	9.58	9.43	ns
16 mA	–1	0.52	6.04	0.03	1.02	0.34	6.15	6.02	3.13	3.30	7.98	7.86	ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 for derating values.

Table 2-53. 1.8V LVCMOS High Slew Worst Military-Case Conditions: T_J = 125°C, Worst-Case VCC = 1.425V, Worst-Case VCCxxxxIOBx = 1.7V Applicable to MSS I/O Banks
Drive  Strength	Speed Grade	t_DOUT	t_DP	t_DIN	t_PY	t_PYS	t_EOUT	t_ZL	t_ZH	t_LZ	t_HZ	Units
4 mA¹	Std.	0.23	2.97	0.09	1.17	1.75	0.23	3.02	2.92	2.36	2.41	ns
4 mA¹	–1	0.19	2.47	0.08	0.98	1.46	0.19	2.52	2.43	1.97	2.00	ns

Note:

Denotes the software default selection. This note is applicable for the entire row.
For specific junction temperature and voltage supply levels, refer to Table 2-7 for derating values.

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