23.22.10 PMC Clock Generator PLLA Register
Possible limitations on PLLA input frequencies and multiplier factors should be checked before using the PMC.
Warning: Bit 29 must always be
set to ‘1’ when programming the CKGR_PLLAR.
This register can only be written if the WPEN bit is cleared in the PMC Write Protection Mode Register.
| Name: | CKGR_PLLAR |
| Offset: | 0x0028 |
| Reset: | 0x20003F00 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ONE | MULA[10:8] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 1 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MULA[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PLLACOUNT[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 1 | 1 | 1 | 1 | 1 | 1 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIVA[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 29 – ONE Must Be Set to 1
Bit 29 must always be set to ‘1’ when programming the CKGR_PLLAR.
Bits 26:16 – MULA[10:0] PLLA Multiplier
Unlisted values are forbidden.
| Value | Description |
|---|---|
| 0 | The PLLA is disabled (PLLA also disabled if DIVA = 0). |
| 1 up to 62 | PLLCK frequency is the PLLA input frequency multiplied by MULA + 1. |
Bits 13:8 – PLLACOUNT[5:0] PLLA Counter
Specifies the number of SLOW_CLK cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written.
Bits 7:0 – DIVA[7:0] PLLA Front End Divider
| Value | Name | Description |
|---|---|---|
| 0 | 0 | PLLA is disabled. |
| 1 | BYPASS | Divider is bypassed (divide by 1) and PLLA is enabled. |
| 2–255 | - | Divider output is the selected clock divided by DIVA. |