3.4.3.9.1 SFR Operation

In this SFR interface, the values for the cache and tag memory are written first and are then transferred to the associated memory when the cache or tag control register is written. The control register contains the READ, WRITE and COMPARE directives along with the destination address. This allows all 128 bits of cache data to remain coherent. The stream buffer registers will be written in a similar fashion, where the register element data will be written first and set into hardware when the ISB address/control register is written.

When reading from the cache or tag memory, the address/control register is written to with the READ bit set. This action will cause the contents of the address memory to be placed into the associated data registers for that memory unit.

Additionally, a data comparison value via the DATA registers set is provided that allows the contents of a cache or tag memory to be compared with a stored value. The result of the comparison will set or clear the Fault flag for the operation in the cache status register. The comparison bits will be separated from a normal Fault, so the result of the comparison operation is not affected by the next normal access to the cache memory.

Writing to the Address/Control register (CACHECTRL) will clear previous Faults in the status register for this action. The Fault bits will not be set by the action of writing unless the address of the cache is out of range. For the data being written or read to be correlated to the correct address, it is up to the user to determine that the TAG address/location is correct for the accessed cache RAM location.