3.4.3.9 SFR-Based Memory Access

The following interface provides a method to understand both cache values (four 32-bit words), the associated TAG addresses (one 32-bit word) for the cache, and ISB stream buffer registers. This interface will also provide a means to compare a given value in each of the memory areas against a value held in a register for testing and hardware validation.

The data register is used to write the instruction data to the cache RAM, and it will also serve as the compare value register. The hardware will generate the EVEN parity bit and use it as part of the comparison operation. If a comparison fails, the current values in the data/comparison registers can then be written back to the cache for continued testing.

Parity Fault assertions can be generated by the use of a control bit that forces the parity bit to an odd parity.