External Signal Source Mode

When the CIC filter is configured for external signal source mode (INSRC(CICCON1[31]) = 0), the filter's input is provided internally by the ADC. The RDCINSEL register is configured as described in ADC Input Selection and Coherent Demodulation, to select the appropriate ADC instance and its corresponding channel for sampling the resolver signals. Refer to the ADC chapter for its configuration details and for selecting the RDC module as the trigger source for conversions.

In external signal source mode, any writes to the CICxDIN register and the CICUPDATE bit are ignored.

In summary, here are the steps to execute the CIC filter in external signal source mode:

  1. Write INSRC(CICCON1[31]) bit to '0'.
  2. Load DECIM(CICDECIM[11:0]) bits with filter length-1. For example, if the filter length is four, then load DECIM with three.
  3. Set the filter order in ORDER(CICCON1[8]).
  4. If demodulation is required, set DEMODEN(CICON[29]) bit. If POLSEL(CICCON1[30]) = 1, the demodulation will be based on the polarity of the excitation signal.
  5. Set the channel enable bits, CH0EN and CH1EN. Turn on the CIC filter, ON(CICCON1[15]).
  6. Configure the RDCINSEL register by setting the IMUXx and ICHANx bits according to the specific ADC module instance and its channel that provides input samples to the CIC channels.
  7. Configure the ADC at the required sampling rate with RDC as its trigger source.
  8. Configure RDCEXCCON, RDCEXCDLY, and RDCCON registers to generate the excitation signal.
  9. The ADC will feed the digital samples to CIC channels.
  10. The CIC filter expects a signed input. When operating in external source mode, if it is connected to an ADC only capable of providing unsigned outputs, the ISIGN0(RDCINSEL[8]) and ISIGN1(RDCINSEL[24]) bits may be used to change the output representation of the inputs. Setting the ISIGNx bit will convert the input samples to signed format by inverting the upper bit of the input sample on channel x. The ADC of the dsPIC33AK256MPS306 family of devices is capable of producing both unsigned and signed samples.
  11. Once the DECIMCNT bit becomes zero, the CIC filter updates CICxACC with the total sum of input samples. Following this, the DONE bit is set, and the CICOSRIF interrupt flag triggers an interrupt event.
  12. The DONE bit will get cleared once the CICxDOUT register is read.

In external source mode, the CIC filter requires input samples on both channels for processing. Users can configure a timeout between these filter samples using the CIC timer, which is enabled when FILTOEN(CICCON1[5]) is set and FILTOPR(CICTIMEOUT[15:3]) is non-zero. The counter FILTOCNT(CICTIMEOUT[31:16]) will begin counting when the first data is received from the ADC on any CIC input channel. If the counter value counts FILTOPR cycles before the data input is available on the other enabled channel, the FILTOERR(CICSTAT[19]) bit will be set, and an error interrupt will be triggered. The counter will stop when valid data input on the other CIC channel is asserted by the ADC.

If one of the CIC channels receives a new ADC input sample before the other channel receives its corresponding sample, then the CICINOVF(RDCSTAT[0]) error bit will be set to indicate that an input overflow has occurred, which also triggers an RDCERRIF interrupt. This signifies a misconfiguration of the ADC channels, and it's the user's responsibility to ensure proper configuration.