20.4.16 Position Counter Initialization Modes

By using the PIMOD[2:0] bits in the QEIx Control register (QEIxCON[12:10]), the user application can specify how the Position Counter is initialized during the module operation.

Mode 0 – The Position Counter is unaffected by the index input.
Mode 1 – The Position Counter is cleared whenever an index input event is detected.
Mode 2 – The Position Counter is initialized with the contents of the QEIxINIT register on the next detected index input event. When the index event occurs, the PIMOD[2:0] bits are cleared and then the counter operates in Mode 0.
Mode 3 – The Position Counter is initialized with the contents of the QEIxINIT register on the next detected index input event following the assertion of the home input. When an index event occurs following the home event, the PIMOD[2:0] bits are cleared and then the counter operates in Mode 0.
Mode 4 – The Position Counter is initialized with the contents of the QEIxINIT register on the second detected index input event following the assertion of the home input. When the second index event occurs following the home event, the PIMOD[2:0] bits are cleared and then the counter operates in Mode 0.
Mode 5 – The Position Counter is cleared when the Position Counter value equals the QEIxGEC register value.
Mode 6 – The Position Counter is loaded with the contents of the QEIxLEC register when the Position Counter value equals the QEIxGEC register value and a count up pulse is detected. The counter is loaded with the contents of the QEIxGEC register when the Position Counter value equals the QEIxLEC register value and a count down pulse is detected.
Mode 7 – The Position Counter is loaded with the contents of the QEIxLEC register when the Position Counter equals the QEIxGEC register’s contents and a count up pulse is detected. The Position Counter is loaded with the contents of the QEIxGEC register when the Position Counter equals the QEIxLEC register contents and a count down pulse is detected. If an index pulse is detected, the Position Counter is loaded with the content of the QEIxLEC register.

Table 20-4. PIMOD Supports in Varies Mode^{(2), (3)}
PIMOD[2:0]	QEI Mode	Hall Mode	Comments
Mode 0	Yes	Yes⁽¹⁾	An index input event does not affect position counter.
Mode 1	Yes	No	Every index input event resets the position counter.
Mode 2	Yes	No	Next index input event initializes the position counter with contents of INIT register.
Mode 3	Yes	No	First Index event after home event initializes position counter with contents of INIT register.
Mode 4	Yes	No	Second Index event after home event initializes position counter with contents of INIT register.
Mode 5	Yes	Yes	When the position counter reaches QEICMPH, the position counter becomes zero.
Mode 6	Yes	Yes	Modulo Count mode for position counter
Mode 7	Yes	No	Modulo Count mode for position counter and every index input event resets the position counter.
Note: For CCM = `0`, the index event is the Quadrature state match event generated when QEA and QEB matches IMV[1:0] bits. The QEA and QEB inputs are decoded to generate count pulses for the QEI mode position counter. The QEA , QEB and INDEX/QEC inputs are decoded to generate count pulses for the QEI mode position counter.