20.4.12 Coherent Counter Access

The content of POSxCNT and INDxCNT registers can be coherently read by hardware using the ECAPEN and HCRE bits in the QEIxCON register.

If an external trigger event selected by ECAPEN bit in the QEIxCON register occurs, then the following events occur:

  • POSxHLD and INDXxHLD registers will capture the contents of the POSxCNT and INDXxCNT when the external trigger event occurs and HCRE=1 (Equivalent to software writing HLDREAD = 1).
  • ECAPIRQ flag in the QEIx status register (QEIxSTAT[27]) is set so that software can determine that external capture event has occurred. If the interrupt enable bit (ECAPIEN) is set, an interrupt is generated. The user can write ECAPIRQ flag = 0 to clear the flag.
  • As long as the ECAPIRQ flag is set, further external capture events would be suppressed, so that software can take its time to read POSxCNT and INDXxCNT.