20.4.15 Index Event

When CCM[1:0] = 00 and HALLEN=0 (Quadrature mode), the IMV[1:0] bits in the QEI Control register (QEIxCON[9:8]) specify the state of the QEAx and QEBx input signals required to acknowledge an index event. An index event is accepted when an index pulse occurs while the value of the QEAx and QEBx inputs match the condition set in the IMV[1:0] bits. This prevents further index events from being accepted until the index input signal is deasserted and ensures that only one index event occurs for each index input pulse. Figure 20-10 illustrates the Index Reset Position Counter operation.

When CCM[1:0] = 01, 10 or 11 (count mode), or 00 and HALLEN = 1 (Hall mode), the IMV[1:0] bits are not used for index matching because there is no Quadrature state in this mode.