9.4.7.3 Source Select
The state machine controls the loading of the source select value on each rising
edge of the clock. The value is left-shifted starting from 1 to 4 (the number of
selectable sources) on every clock edge to create a one-hot selection signal for
the analog module. When the source is selected via the state machine round-robin
sequencer, the source is scanned and SCANSRC[2:0] is set once the scan is
complete. After all sources have been scanned and compared against the UV and OV
trip points, SCANSRC[1:0] resets to 0 and then is loaded with 1 on the next
clock. The neutral 0 selection is used as the period during which module
configuration changes can be made. The VMSTAT.WRALLOW bit is set during this
period. After the number of selectable sources is reached, SCANSRC[2:0] is set
to 0b4000 on the final clock, before being reset to 0.
- On each rising edge of the clock, the corresponding VMxSTAT[SCANSRCn] bit is set.
- On each rising edge of the clock, the corresponding VMxEVENT[UVSRCn] bit is set if a UV event occurs.
- On each rising edge of the clock, the corresponding VMxEVENT[OVSRCn] bit is set if an OV event occurs.