3.4.3.7.1 TAG Operation

A cache miss will cause an NVM fetch of a 128-bit cache line into cache RAM. Along with the 4 instructions fetched, a TAG address will be stored. At the time of TAG memory storage, an odd parity bit will be added to the tag memory. This parity will be used when scanning a TAG memory looking for a CPU match address.

When a cache MISS is detected, new data will be fetched from the NVM (flash memory) and the address TAG is written into TAG memory. This write operation will have an odd parity bit generated, concatenated to the address, and stored with each saved address in TAG memory. An odd parity bit has been selected so that a Reset-initialized register value of zero will yield a parity Fault if addressed.

The TPE (TAG Parity Error) bit will be set in the status register. The TAG Parity Error bit will remain set until it is cleared in the status register.