6.3.5.8 PIC32CXMTSH Example Code

#include <stdint.h>

/* This address is in data RAM shared by both cores. */
volatile uint32_t __attribute__((address(0x20088000))) test_shared_variable;

void main(){
    // Assign a different variable to the shared variable
    test_shared_variable = 0xCCCCCCCCu;
    while(1);
    return;
}

#pragma config SECURITY_BIT = CLEAR
#pragma config PLANE_SELECTION = CLEAR
#pragma config ERASE_FUNCTION_LOCK = 0x0 // Enter Hexadecimal value
#pragma config BOOT_MODE = 0x3           // Enter Hexadecimal value

#include <xc.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include "Secondary.h" // Update this with path to secondary project

/* Add an _on_reset() function to initialize the secondary (metrology core).
 * This application-provided function will be called by the default
 * XC32 device startup code provided in the DFP.
 */
void _on_reset()
{
    // Assert the coprocessor core and peripheral reset
    RSTC_REGS->RSTC_MR = RSTC_MR_KEY_PASSWD | (RSTC_REGS->RSTC_MR & ~RSTC_MR_CPROCEN(0b1) & ~RSTC_MR_CPEREN(0b1));
    // Keep the slow clock source or 
    //  select MAINCK as the Subsystem 1 (core and peripheral) clock
    PMC_REGS->PMC_CPU_CKR &= ~PMC_CPU_CKR_CPCSS(0b111);
    // Enable Core 1 system clock (peripheral bus/SRAM) and Core 1 clock:
    PMC_REGS->PMC_SCER |= PMC_SCER_CPKEY_PASSWD | PMC_SCER_CPCK(0b1) | PMC_SCER_CPBMCK(0b1);
    // Delay until clocks are ready
    while ((PMC_REGS->PMC_SR & PMC_SR_CPMCKRDY(0b1)) == 0)
        ;
    // Release Core 1 system reset (peripheral bus/SRAM)
    RSTC_REGS->RSTC_MR |= RSTC_MR_KEY_PASSWD | RSTC_MR_CPEREN(0b1);
    // Configure the Subsystem 1 (core and peripheral) clock 
    //  to a higher speed and select it as source clock
    PMC_REGS->PMC_CPU_CKR |= PMC_SR_CPMCKRDY(0b001);
    // Enable SRAM1 clock
    PMC_REGS->PMC_PCR |= PMC_PCR_CMD(0b1) | PMC_PCR_EN(0b1) | PMC_PCR_PID(0b1011011);
    // Delay until clocks are ready
    while ((PMC_REGS->PMC_SR & PMC_SR_CPMCKRDY(0b1)) == 0)
        ;
}

volatile uint32_t rocco = 0xBEBABAB0;

/* This address is in data RAM shared by both cores. */
volatile uint32_t __attribute__((address(0x20088000))) test_shared_variable;

/* Use 'manual' mode. This means that we need a function call to copy the
 * secondary-core image to the shared RAM.
 */
#define MANUAL_INIT 1

int main()
{
    // Initialize the shared variable with a value.
    test_shared_variable = 0xABADBADEu;

    // Note: Enable this call when using 'manual' mode. Manual mode means that
    // the secondary-core image has not been automatically copied by data init.
#if MANUAL_INIT
    __xc32_LoadAllSecondarySections();
#endif

    // Release the Core 1 from reset.
    RSTC_REGS->RSTC_MR |= RSTC_MR_KEY_PASSWD | RSTC_MR_CPROCEN(0b1);

    while (1)
    {
    }

    return (EXIT_SUCCESS);
}