17.4.7.1 ECC Error Injection

Injecting a single- or double-bit error into the data written to RAM can test the ECC logic. Subsequent RAM read will generate an ECC error, either a single-bit correction, double-bit non-correctable, or an ECC checker comparator error. These errors are flagged in INTFLAGS.

A single-bit or double-bit ECC error is injected by writing a ‘1’ to the ECC1 bit or ECC2 bit in the CTRLA register and then performing a store instruction to an address in RAM. A subsequent load instruction from this address will result in a single-bit or double-bit ECC error being reported in the INTFLAGS. Single-bit errors are injected in the data LSB resulting in a SYNDROME value of 0. With double-bit error injection, the MSB of the ECC parity data is additionally modified. In this case, the SYNDROME value is invalid since the ECC can only detect the presence of double-bit errors, not the location. ECC error injection must be performed with global interrupts disabled to ensure that the error is not accidentally injected in the wrong data. In a system with additional active bus hosts, such as a DMA controller, these bus hosts must be kept from accessing the RAM during the error injection sequence to protect against errors injected into accesses from unintended bus hosts.

An ECC checker comparator mismatch error injection is enabled by writing a ‘1’ to the COMP bit in the CTRLA register. The following read access will result in a mismatch between the duplicated ECC checkers, resulting in the setting of the COMP bit in the INTFLAGS register.