17.4.7.2 Parity Error Injection

Parity errors can be injected into data output on the data bus (i.e., a load instruction from the CPU) by writing a ‘1’ to the PARITY bit in the CTRLA register.

To test the parity error on the load address, force the CPU to inject a parity error on the address bus on the next data bus access by writing a ‘1’ to the INJPDA bit in the CPU.CTRLA register.

To test the parity error on the data to be stored in RAM, configure the CPU to inject a parity error on the data bus on the next data bus write access by writing a ‘1’ to the INJPDD bit in the CPU.CTRLA register.

Writing a ‘1’ to the INJPDC bit in the CPU.CTRLA register can also inject an error into the control signals.