16.3.9.2 Parity Error Injection

Parity errors can be injected on data sent to the data bus (i.e., a load or fetch instruction from the CPU) by setting the PARITYD or PARITYI bits in the CTRLD register.

To test parity error on fetch address, have the CPU inject a parity error on the fetch address by setting the PINJI bit in the CPU.CTRLA register.

To test parity error on data to be stored in NVM, have the CPU inject a parity error on the write data in an ST/SPM instruction by setting the PINJDD bit in the CPU.CTRLA register. A parity error will also return a bus error to the initiator, setting appropriate flags in the initiator. If the CPU is used as an initiator, the BUSERR bit in the CPU.INTFLAGS register is set.