16.3.9.1 ECC Error Injection

Test the ECC logic by injecting single- or double-bit errors into the data read from Flash or EEPROM. An NVM read access (instruction fetch or Flash/EEPROM data) will generate ECC errors, either single-bit corrections or double-bit uncorrectable errors, that are flagged in the INTFLAGSB register.

Error injection will cause flags in the INTFLAGSB register to be set and trigger an interrupt request. An ECC2 error will also return a bus error to the initiator, setting appropriate flags in the initiator (if the CPU is used as the initiator, BUSERR in CPU.INTFLAGS is set), requesting action from the Error Controller and the Interrupt Controller. Interrupt response after error injection can be prevented by:

1. Masking interrupt requests from the INTFLAGSB register by clearing the I bit in the CPU.SREG register.
2. Disabling the interrupt request from the initiator. If the CPU is the initiator, this requires setting the NMIDIS bit in the CPU.CTRLA register (since the CPU.INTFLAGS register is connected as NMI).
3. Configuring the relevant Error Controller channels to severity NOTIFICATION.

ECC error injection is enabled by setting the ECC1 or ECC2 bits in the Control D (CTRLD) register to ‘1’. The next Flash or EEPROM access on the data interface (i.e., LD or LPM) will have a bit error in bit number ‘0’ (the LSb). If ECC2 is set, a bit error will, in addition, be injected in the global parity bit (the MSb in the Bit Addressing of ECC Errors table in the Error Bit Addressing section), in other words, a 2-bit error. The bit numbers to insert errors into are hard-coded and not user-selectable to save hardware. The added flexibility of user-addressable bit locations is unnecessary since the ECC checkers are duplicated (hardware redundancy).

ECC checker comparator mismatch error injection is enabled by setting the COMP bit in the CTRLD register to ‘1’ and CTRLD.DATA to the desired value. The next NVM access will result in a mismatch between the duplicated ECC checkers.