54.15 Rev G - 04/2015

2 Ordering Information	Added Device Identification.
6 I/O Multiplexing and Considerations	New sections added: 6.2.3 SERCOM I²C Pins: Information moved from the "Type" column in Table 6-2 into separate table. Updated CCL column. 6.2.4 GPIO Clusters: Moved from 45.2 Absolute Maximum Ratings. 6.2.5 TCC Configurations: Moved from 36 Timer/Counter for Control Applications (TCC).
9 Memories	Updated Table 9-4. Updated Table 9-1.
11 PAC - Peripheral Access Controller	Register bit correction: INTFLAGAHB, INTFLAGA, INTFLAGB, INTFLAGC, STATUSA, STATUSB and STATUSC
13 DSU - Device Service Unit	Table 13-6 updated: MBIST is not available when the device is protected from the external address space.
16 GCLK - Generic Clock Controller	16.3 Block Diagram: GCLK_MAIN goes into the MCLK, not the PM. 16.4 Signal Description: Available signals are GCLK_IO[7:0].
17 MCLK – Main Clock	Updated block diagram in 17.6.2.4 Selecting the Synchronous Clock Division Ratio.
20 OSCCTRL – Oscillators Controller	Added OSC48M Calibration (CAL48M) register added (only available for Rev D silicon).
22 SUPC – Supply Controller	Updated VREF.SEL bit selection table. Removed references to BODCORE register and bit descriptions and updated description in 22.6.3.4 VDDCORE Brown-Out Detector (BODCORE).
19 PM - Power Manager	Sleep modes: Removed references to IDLE0 and IDLE1. Renamed IDLE2 to IDLE.
25 DMAC – Direct Memory Access Controller	CTRL.CRCENABLE bit added in bit position 2.
27 NVMCTRL – Nonvolatile Memory Controller	CTRLB27.8.2 Control B.CACHEDIS: Updated from one bit in postion 18 to two bits in position 19:18. Updated bit description and bit value settings.
32 SERCOM SPI – SERCOM Serial Peripheral Interface	32.2 Features: Updated references to serial clock speed in master and slave operation.
34 CAN - Control Area Network (SAM C21 Only)	CREL34.8.1 Core Release: Updated reset value from 0x31000000 (device rev B) to 0x32100000 (device rev C and newer).
35 Timer/Counter (TC)	Added register property "Write-Synchronized" to the CCBUFx and PERBUF registers.
36 Timer/Counter for Control Applications (TCC)	Updated number of TCC instances from one to three. 36.6.2.4 Counter Operation: 'Stop Command and Event Action' split into 'Stop Command' and 'Pause Event Action' 36.6.2.7 Capture Operations: Value 0 in CAPTMIN mode is captured only in down-counting mode. 36.6.3.4 Ramp Operations: RAMP2C Operation added. 36.6.2.5 Compare Operations: Reorganization of section. Corrected bit names in the WAVE register: CIRCCENx -> CICCENx and CIRPEREN -> CIPEREN.
37 Configurable Custom Logic (CCL)	Number of LUTCTRL registers changed from eight to four. Number of SEQCTRL registers changed from four to two. 37.6.2.4 Truth Table Inputs Selection: Updated description and figure in Analog Comparator Inputs (AC).
39 SDADC – Sigma-Delta Analog-to-Digital Converter (SAM C21 only)	Resolution corrected from 24-bit to 16-bit. Conversion range updated from "0V to V_ref"to "0V to 0.7xV_ref" Test Mode section removed. Updated operation formula in the following registers: OFFSETCORR39.8.14 Offset Correction GAINCORR39.8.15 Gain Correction SHIFTCORR39.8.16 Shift Correction Updated RESULT bit description in RESULT39.8.19 Result.
40 AC – Analog Comparators	COMPCTRL40.8.12 Comparator Control n: SPEED bit description updated. Values 0x1 and 0x2 is reserved.
41 DAC – Digital-to-Analog Converter (SAM C21 only)	Updated DATA register: DATA bits access corrected from read/write (R/W) to write (W).TPUBSAMD-354
43 TSENS – Temperature Sensor	43.6.2.3 Measurement: Added temperature measurement recommendation to avoid discrepancies.
45 Electrical Characteristics 85°C (SAM C20/C21 E/G/J)	Added electrical characteristics for 85°C. 6.2.4 GPIO Clusters moved to 6 I/O Multiplexing and Considerations.
46 Electrical Characteristics 105°C (SAM C20/C21 E/G/J)	Added electrical characteristics for 105°C.
52 Packaging Information	Updated package drawings to include GPC, drawing no. and revision letter.
Errata SAM C20 and Errata SAM C21	Updated revision B errata: Added Errata reference 14497, 14633 and 15342. Added revision C errata. Added revision D errata.

2 Ordering Information

Added Device Identification.

6 I/O Multiplexing and Considerations

New sections added:

6.2.3 SERCOM I²C Pins: Information moved from the "Type" column in Table 6-2 into separate table.
Updated CCL column.
6.2.4 GPIO Clusters: Moved from 45.2 Absolute Maximum Ratings.
6.2.5 TCC Configurations: Moved from 36 Timer/Counter for Control Applications (TCC).

9 Memories

Updated Table 9-4.
Updated Table 9-1.

11 PAC - Peripheral Access Controller

Register bit correction: INTFLAGAHB, INTFLAGA, INTFLAGB, INTFLAGC, STATUSA, STATUSB and STATUSC

13 DSU - Device Service Unit

Table 13-6 updated: MBIST is not available when the device is protected from the external address space.

16 GCLK - Generic Clock Controller

16.3 Block Diagram: GCLK_MAIN goes into the MCLK, not the PM.
16.4 Signal Description: Available signals are GCLK_IO[7:0].

17 MCLK – Main Clock

Updated block diagram in 17.6.2.4 Selecting the Synchronous Clock Division Ratio.

20 OSCCTRL – Oscillators Controller

Added OSC48M Calibration (CAL48M) register added (only available for Rev D silicon).

22 SUPC – Supply Controller

Updated VREF.SEL bit selection table.
Removed references to BODCORE register and bit descriptions and updated description in 22.6.3.4 VDDCORE Brown-Out Detector (BODCORE).

19 PM - Power Manager

Sleep modes: Removed references to IDLE0 and IDLE1. Renamed IDLE2 to IDLE.

25 DMAC – Direct Memory Access Controller

CTRL.CRCENABLE bit added in bit position 2.

27 NVMCTRL – Nonvolatile Memory Controller

CTRLB27.8.2 Control B.CACHEDIS: Updated from one bit in postion 18 to two bits in position 19:18. Updated bit description and bit value settings.

32 SERCOM SPI – SERCOM Serial Peripheral Interface

32.2 Features: Updated references to serial clock speed in master and slave operation.

34 CAN - Control Area Network (SAM C21 Only)

CREL34.8.1 Core Release: Updated reset value from 0x31000000 (device rev B) to 0x32100000 (device rev C and newer).

35 Timer/Counter (TC)

Added register property "Write-Synchronized" to the CCBUFx and PERBUF registers.

36 Timer/Counter for Control Applications (TCC)

Updated number of TCC instances from one to three.
36.6.2.4 Counter Operation: 'Stop Command and Event Action' split into 'Stop Command' and 'Pause Event Action'
36.6.2.7 Capture Operations: Value 0 in CAPTMIN mode is captured only in down-counting mode.
36.6.3.4 Ramp Operations: RAMP2C Operation added.
36.6.2.5 Compare Operations: Reorganization of section.
Corrected bit names in the WAVE register: CIRCCENx -> CICCENx and CIRPEREN -> CIPEREN.

37 Configurable Custom Logic (CCL)

Number of LUTCTRL registers changed from eight to four.
Number of SEQCTRL registers changed from four to two.
37.6.2.4 Truth Table Inputs Selection: Updated description and figure in Analog Comparator Inputs (AC).

39 SDADC – Sigma-Delta Analog-to-Digital Converter (SAM C21 only)