54.2 Revision J - 12/2021
The following updates were added in this revision of the document.
| Section | Updates |
|---|---|
| Features | Added new 64 MHz information |
| Configuration Summary | Added new 64 MHz information and new notes to the tables. |
| Ordering Information | Added information related to the new 64 MHz packages. |
| Block Diagram | Updated the Processor section of the Diagram to denote both 48 MHz and 64 MHz parts. |
| PM - Power Manager | Updated the table in Regulator Automatic Low Power Mode with a new note. |
| SUPC - Supply Controller |
|
| DMAC - Direct Memory Access Controller | Updated Addressing with a new Register name. |
| PORT - I/O Pin Controller |
|
| EVSYS - Event System | Added the CHANNELn.PATH column to the table in Sleep Mode Operation. |
| CAN - Controller Area Network | Updated the TSCV Register to properly display the TSC bitfield. |
| ADC - Analog-to-Digital Controller | Removed an erroneous reference to OPAMP from Features. |
| Electrical Characteristics at 85°C (SAM C20/C21 E/G/J) |
|
| Electrical Characteristics at 105°C (SAM C20/C21 E/G/J) |
|
| Electrical Characteristics AEC-Q100 Grade 1, 125°C (SAM C20/C21 E/G/J) | Updated table 48-32 with new information and notes in 48 MHz RC Oscillator (OSC48M) Characteristics. |
| Packaging Information | Added a new note applicable to the QFN packages with an exposed die to Package Drawings. |
| Schematic Checklist |