23.6.17 Compare/Capture Channel n
The Compare/Capture Channel n (CCn) register holds the 16-bit CCn value. The register has two functions, depending on the mode of operation.
For capture operation, this register represents the second buffer level and access point for the CPU and DMA.
For compare operation, this register is continuously compared to the counter value. Normally, the output form the comparator is then used for generating waveforms.
The CCn register is updated with the buffer value from its corresponding Compare/Capture Channel n Buffer (CCBUFn) register when an UPDATE condition occurs.
Note: In match frequency operation, the CC0 register controls the counter
period.
Note: This register is write-synchronized. The CCn Synchronization Busy bit of
the Synchronization Busy register (SYNCBUSY.CCn) must be checked to ensure that the CCn
register synchronization is complete.
| Name: | CC[n] |
| Offset: | 0x44 + n*0x04 [n=0..3] |
| Reset: | 0x00000000 |
| Property: | Write-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CC[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CC[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – CC[15:0] Compare/Capture Channel Value
This bit field holds the value of the Compare/Capture Channel.