23.6.12 Interrupt Flag Status and Clear
| Name: | INTFLAG |
| Offset: | 0x2C |
| Reset: | 0x00000000 |
| Property: | – |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MC3 | MC2 | MC1 | MC0 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FAULT1 | FAULT0 | FAULTB | FAULTA | DFS | UFS | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERR | CNT | TRG | OVF | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 16, 17, 18, 19 – MCn Match or Capture Channel n Interrupt Flag
This flag is set after a match with the compare condition or once the CCn register contains a
valid capture value, and will generate an interrupt request if INTENSET.MCn =
‘1’.
Writing a ‘0’ to one of these bits has no effect.
Writing a ‘1’ to one of these bits will clear the corresponding Match or Capture Channel n interrupt flag.
In Capture operation, this flag is automatically cleared when the CCn register is read.
Bits 14, 15 – FAULTn Non-Recoverable Fault n Interrupt Flag
This flag is set after a Non-Recoverable Fault n occurs, and will generate an interrupt request if INTENSET.FAULTn = ‘1’.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Non-Recoverable Fault n interrupt flag.
Bits 12, 13 – FAULTx Recoverable Fault x Interrupt Flag
This flag is set after a Recoverable Fault x occurs, and will generate an interrupt request if INTENSET.FAULTx = ‘1’.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Non-Recoverable Fault x interrupt flag.
Bit 11 – DFS Non-Recoverable Debug Fault State Interrupt Flag
This flag is set after a Debug Fault State occurs, and will generate an interrupt request if INTENSET.DFS = ‘1’.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Debug Fault State interrupt flag.
Bit 10 – UFS Non-Recoverable Update Fault
This flag is set when the RAMP index changes and the Lock Update bit is set (CTRLBSET.LUPD = ‘1’), and will generate an interrupt request if INTENSET.UFS = ‘1’.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Non-Recoverable Update Fault interrupt flag.
Bit 3 – ERR Error Interrupt Flag
This flag is set if a new capture occurs on a channel when the corresponding Match or Capture Channel x interrupt flag = ‘1’. This means that it is not possible to save the new capture value, and it will generate an interrupt request if INTENSET.ERR = ‘1’.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Error Interrupt flag.
Bit 2 – CNT Counter Interrupt Flag
This flag is set after a counter event occurs, and it will generate an interrupt request if INTENSET.CNT = ‘1’.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the CNT Interrupt flag.
Bit 1 – TRG Retrigger Interrupt Flag
This flag is set after a counter retrigger occurs, and it will generate an interrupt request if INTENSET.TRG = ‘1’.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Retrigger Interrupt flag.
Bit 0 – OVF Overflow Interrupt Flag
This flag is set after an overflow condition occurs, and it will generate an interrupt request if INTENSET.OVF = ‘1’.
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit clears the Overflow Interrupt flag.