23.6.14 Counter
Note:
- Prior to any read access, this register
must be manually read synchronized by writing to the TCC Command bit in the Control B
Set register (CTRLBSET.CMD = READSYNC) and wait for the manual read synchronization to
finish (SYNCBUSY.CTRLB and CTRLBSET.CMD are ‘
0’). - This register is write-synchronized. The COUNT Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.COUNT) must be checked to ensure that the COUNT register write synchronization is complete.
| Name: | COUNT |
| Offset: | 0x34 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Write-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| COUNT[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| COUNT[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – COUNT[15:0] Counter Value
This bit field hold the value of the Counter Value register.