23.6.21 Compare/Capture Channel n Buffer
The Compare/Capture Channel n Buffer (CCBUFn) register serves as the buffer for the associated
Compare/Capture Channel n (CCn) register. The CCBUFn register value is copied to the CCn
register on an UPDATE condition or when writing the Update command to the Command bit field
in the Control B Set register (CTRLBSET.CMD = UPDATE).
Note:
- This register is write-synchronized. The CCn Synchronization Busy bit in the Synchronization Busy register (SYNCBUSY.CCn) must be checked to ensure that synchronization of the CCn register is complete..
- This register must be written with 32-bit access only (no 8- or 16-bit writes)
- Accessing this register using the CPU or DMA will affect the corresponding Compare/Capture Channel n Buffer Valid bit in the Status register (STATUS.CCBUFVn)
| Name: | CCBUF[n] |
| Offset: | 0x70 + n*0x04 [n=0..3] |
| Reset: | 0x00000000 |
| Property: | Write-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CCBUF[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CCBUF[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 15:0 – CCBUF[15:0] Compare/Capture Channel Buffer Value
This bit field holds the Compare/Capture Channel Buffer Value.