23.6.8 Debug control
| Name: | DBGCTRL |
| Offset: | 0x1E |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FDDBD | DBGRUN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 2 – FDDBD Fault Detection on Debug Break Detection
This bit is not affected by a software reset and should not be changed by software while the TCC is enabled.
By default, this bit is zero, and the on-chip debug (OCD) fault protection is disabled.
When writing a '1'to this bit, an OCD break request from the OCD
system will trigger a non-recoverable fault. When this bit is set, OCD fault
protection is enabled, and any OCD break request from the OCD system will trigger a
non-recoverable fault.
| Value | Description |
|---|---|
| 0 | No faults are generated when the TCC is halted in Debug mode |
| 1 | A non recoverable fault is generated, and FAULTD flag is set when the TCC is halted in Debug mode |
Bit 0 – DBGRUN Debug Running State
This bit is affected by system software Reset and should not be changed by software while the TCC is enabled.
| Value | Description |
|---|---|
| 0 | The TCC is halted when the device is halted in Debug mode |
| 1 | The TCC continues normal operation when the Device is halted in Debug mode |