23.6.9 Event Control


Bit	31	30	29	28	27	26	25	24
					MCEO3	MCEO2	MCEO1	MCEO0
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	23	22	21	20	19	18	17	16
					MCEI3	MCEI2	MCEI1	MCEI0
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	15	14	13	12	11	10	9	8
	TCEI1	TCEI0	TCINV1	TCINV0		CNTEO	TRGEO	OVFEO
Access	R/W	R/W	R/W	R/W		R/W	R/W	R/W
Reset	0	0	0	0		0	0	0


Bit	7	6	5	4	3	2	1	0
	CNTSEL[1:0]		EVACT1[2:0]			EVACT0[2:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 24, 25, 26, 27 – MCEOn Match or Capture Channel n Event Output Enable

These bits control whether the match/capture event on channel n is enabled and will be generated for every match or capture.

Value	Description
0	The match/capture x event is disabled and will not be generated
1	The match/capture x event is enabled and will be generated for every compare or capture on channel n

Bits 16, 17, 18, 19 – MCEIn Match or Capture Channel n Event Input Enable

These bits indicate whether the match/capture n incoming event is enabled.

These bits are used to enable match or capture input events to the CCn channel of the TCC and to enable recoverable Faults A and B.

Value	Description
0	Incoming events are disabled
1	Incoming events are enabled

Bits 14, 15 – TCEIn Timer/Counter Event Input n Enable

This bit is used to enable input event n to the TCC.

Value	Description
0	Incoming event n is disabled
1	Incoming event n is enabled

Bits 12, 13 – TCINVn Timer/Counter Event n Invert Enable

This bit inverts the event n input.

Value	Description
0	Input event source n is not inverted
1	Input event source n is inverted

Bit 10 – CNTEO Timer/Counter Event Output Enable

This bit is used to enable the counter cycle event. When enabled, an event will be generated at the beginning or end of the counter cycle depending on the CNTSEL[1:0] settings.

Value	Description
0	The Counter cycle output event is disabled and will not be generated
1	The Counter cycle output event is enabled and will be generated depending on the CNTSEL[1:0] value

Bit 9 – TRGEO Retrigger Event Output Enable

This bit is used to enable the counter retrigger event. When enabled, an event will be generated when the counter retriggers.

Value	Description
0	The counter retrigger event is disabled and will not be generated
1	The counter retrigger event is enabled and will be generated for every counter retrigger

Bit 8 – OVFEO Overflow/Underflow Event Output Enable

This bit is used to enable the overflow/underflow event. When enabled, an event will be generated when the counter reaches the TOP or ZERO value.

Value	Description
0	The overflow/underflow counter event is disabled and will not be generated
1	The overflow/underflow counter event is enabled and will be generated for every counter overflow or underflow

Bits 7:6 – CNTSEL[1:0] Timer/Counter Interrupt and Event Output Selection

These bits define on which part of the counter cycle the counter event output is generated.

Value	Name	Description
0x0	START	An interrupt/event is generated at the beginning of each counter cycle
0x1	END	An interrupt/event is generated at the end of each counter cycle
0x3	BOUNDARY	An interrupt/event is generated at the beginning of the first counter cycle, and at the end of last counter cycle
Other	—	Reserved

Bits 5:3 – EVACT1[2:0] Timer/Counter Event Input 1 Action

This bit field defines the action the TCC will perform on the TCEI1 event input.

Value	Name	Description
0x0	OFF	Event action disabled
0x1	RETRIGGER	Restart or retrigger TCC on event
0x2	DIR	Direction control
0x3	STOP	Stop TCC on event
0x4	DEC	Decrement TCC on event
0x6	PWP	Period captured into CC1 Pulse Width on CC0
0x7	FAULT	Non-recoverable fault
Other	—	Reserved

Bits 2:0 – EVACT0[2:0] Timer/Counter Event Input 0 Action

This bit field defines the action the TCC will perform on the TCEI0 event input 0.

Value	Name	Description
0x0	OFF	Event action disabled
0x1	RETRIGGER	Restart or retrigger TCC on event
0x2	COUNTEV	Count on event
0x3	START	Start TCC on event
0x4	INC	Increment TCC on event
0x5	COUNT	Count on the active state of an asynchronous event
0x6	STAMP	Capture Time-stamp (overflow)
0x7	FAULT	Non-recoverable fault
Other	—	Reserved

Name:	EVCTRL
Offset:	0x20
Reset:	0x00000000
Property:	PAC Write-Protection, Enable-Protected