23.6.13 Status
| Name: | STATUS |
| Offset: | 0x30 |
| Reset: | 0x00000001 |
| Property: | Read-Synchronized, Write-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CMP3 | CMP2 | CMP1 | CMP0 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CCBUFV3 | CCBUFV2 | CCBUFV1 | CCBUFV0 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FAULT1 | FAULT0 | FAULTB | FAULTA | FAULT1IN | FAULT0IN | FAULTBIN | FAULTAIN | ||
| Access | R/W | R/W | R/W | R/W | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PERBUFV | PATTBUFV | DFS | UFS | IDX | STOP | ||||
| Access | R/W | R/W | R/W | R/W | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 1 |
Bits 24, 25, 26, 27 – CMPn Compare Channel n Value
This bit reflects the channel n output compare value.
| Value | Description |
|---|---|
| 0 | Channel compare output value is 0 |
| 1 | Channel compare output value is 1 |
Bits 16, 17, 18, 19 – CCBUFVn Compare/Capture Channel n Buffer Valid
For compare channel:
This bit is set when a new value is written to the corresponding CCBUFn register.
This bit is cleared either by writing a ‘1’ to the corresponding location when
the CTRLB.LUPD is set, or automatically on an UPDATE condition.
For capture channel:
This bit is set when a valid capture value is stored in the CCBUFn register.
This bit is automatically cleared when the CCBUF value is copied into its CCn register.
Bits 14, 15 – FAULTn Non-recoverable Fault n State
This bit is set as soon as a non-recoverable Fault n condition occurs.
This bit is cleared by writing a ‘1’ to this bit and the
corresponding FAULTnIN status bit is ‘0’.
Once this bit is clear, the timer/counter will restart from the last COUNT value. To restart the timer/counter from BOTTOM, the timer/counter restart command must be executed before clearing the corresponding STATEn bit. For further details on timer/counter commands, refer to the commands listed in the TCC Command bit field of the Control B Set (CTRLBSET.CMD) register.
Bits 12, 13 – FAULTx Recoverable Fault x State
This bit is set as soon as recoverable Fault x condition occurs.
This bit is cleared when Fault B action is resumed, or by writing a
‘1’ to this bit when the corresponding FAULTxIN bit is low.
If the software halt command is enabled (FAULTB.HALT = SW), clearing this bit
will release the timer/counter.
Bits 10, 11 – FAULTnIN Non-Recoverable Fault n Input
This bit is set while an active Non-Recoverable Fault n input is present.
Bits 8, 9 – FAULTxIN Recoverable Fault x Input
This bit is set while an active Recoverable Fault x input is present.
Bit 7 – PERBUFV Period Buffer Valid
This bit is set when a new value is written to the PERBUF register.
This bit is cleared on an UPDATE condition when the Lock Update bit in the Control B (CTRLB.LUPD) register is set, or by writing a ‘1’ to this bit.
Bit 5 – PATTBUFV Pattern Generator Value Buffer Valid
This bit is set when a new value is written to the PATTBUF register.
This bit is cleared on an UPDATE condition when the Lock Update bit in the Control B (CTRLB.LUPD) register is set, or by writing a ‘1’ to this bit.
Bit 3 – DFS Debug Fault State
This bit is set in Debug mode when the Fault Detection on Debug Break Detection bit in the Debug Control (DDBGCTRL.FDDBD) register is set.
This bit is cleared by writing a ‘1’ to it and when the TCC is not in Debug
mode.
When this bit is set, the counter is halted and the Waveforms state depends on the Non-Recoverable State n Output Enable (NREx) bits and the Non-Recoverable State n Output Value (NRVn) bits of the Driver Control (DRVCTRL) register.
Bit 2 – UFS Non-recoverable Update Fault State
This bit is set by hardware when the RAMP index changes and the Lock Update bit is set (CTRLBSET.LUPD). The bit is cleared by writing a one to this bit.
When the bit is set, the waveforms state depend on the DRVCTRL.NRE and DRVCTRL.NRV registers.
Bit 1 – IDX Ramp Index
For RAMP2 operation:
This bit is cleared during cycle A.
This bit is set during cycle B
For RAMP1 operation:
This bit always reads ‘0’.
For details on ramp operations, refer to the Ramp Operations section.
Bit 0 – STOP Stop
This bit is set when the TCC is disabled, either on a STOP command or on an UPDATE condition when One-Shot operation mode is enabled (CTRLBSET.ONESHOT = ‘1’).
This bit is cleared on the next incoming counter increment or decrement.
| Value | Description |
|---|---|
| 0 | Counter is running |
| 1 | Counter is stopped |