23.6.2 Control B Clear

This register allows the user to change its value without performing a read-modify-write operation. Changes in this register will also be reflected in the Control B Set (CTRLBSET) register.

Note: This register is write-synchronized - SYNCBUSY.CTRLB must be checked to ensure that synchronization of the CTRLBCLR register is complete.

Name:	CTRLBCLR
Offset:	0x04
Reset:	0x00
Property:	PAC Write-Protection, Write-Synchronized, Read-Synchronized


Bit	7	6	5	4	3	2	1	0
	CMD[2:0]			IDXCMD[1:0]		ONESHOT	LUPD	DIR
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:5 – CMD[2:0] TCC Command

Writing 0x0 to this bit field has no effect.

Writing a value other than 0x0 to these bit field bits will clear the pending command.

Bits 4:3 – IDXCMD[1:0] Ramp Index Command

This bit field can be used to force cycle A and cycle B changes in all RAMP2 operations. On timer/counter update condition, the command is executed, the IDX flag in the STATUS register is updated, and the IDXCMD command is cleared.

Writing 0x0 to this bit field has no effect.

Writing a value other than 0x0 to this bit field will clear the pending command.

Bit 2 – ONESHOT One-Shot

This bit controls the one-shot operation of the TCC. When one-shot operation is enabled, the TCC will stop counting on the next overflow or underflow condition or upon receiving a stop command.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will disable the one-shot operation.

Value	Description
0	The TCC will update the counter value on overflow or underflow condition and continue operation
1	The TCC will stop counting on the next overflow or underflow condition

Bit 1 – LUPD Lock Update

This bit controls the update operation of the TCC buffered registers.

When the Lock Update bit is cleared, the values of the buffer registers will be copied to their non-buffered counterparts on an UPDATE condition.

This bit has no effect when input capture operation is enabled.

Note:

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit enables buffer registers updates on hardware UPDATE condition.

Value	Description
0	The buffer registers values are copied into the corresponding non-buffer registers on a hardware update condition
1	The buffer registers values are not copied into the corresponding non-buffer registers on a hardware update condition

Bit 0 – DIR Counter Direction

This bit is used to change the direction of the counter.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit will clear the bit and cause the counter to count up.

Value	Description
0	The timer/counter is counting up (incrementing)
1	The timer/counter is counting down (decrementing)