23.6.16 Waveform
| Name: | WAVE |
| Offset: | 0x3C |
| Reset: | 0x00000000 |
| Property: | Write-Synchronized, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| POL3 | POL2 | POL1 | POL0 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CICCEN3 | CICCEN2 | CICCEN1 | CICCEN0 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CIPEREN | RAMP[2:0] | WAVEGEN[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 16, 17, 18, 19 – POLn Channel n Polarity
Setting these bits enables the output polarity in single- and dual-slope PWM and dual-compare operations.
- These bits are not enable-protected
- These bits are write-synchronized. The WAVE Synchronization Busy bit of the Synchronization Busy register (SYNCBUSY.WAVE) must be checked to ensure that the WAVE.POLn synchronization is complete.
Channel n Polarity in Single-Slope Mode
| Value | Name | Description |
|---|---|---|
| 0 | NORMAL | Compare output is initialized to ~DIR and set to DIR when TCC counter matches CCn value. |
| 1 | INVERTED | Compare output is initialized to DIR and set to ~DIR when TCC counter matches CCn value. |
Bits 16, 17, 18, 19 – POLn Channel n Polarity
Setting these bits enables the output polarity in single- and dual-slope PWM and dual-compare operations.
- These bits are not enable-protected
- These bits are write-synchronized. The WAVE Synchronization Busy bit of the Synchronization Busy register (SYNCBUSY.WAVE) must be checked to ensure that the WAVE.POLn synchronization is complete.
Channel n Polarity in Dual-Slope Mode
| Value | Name | Description |
|---|---|---|
| 0 | NORMAL | Compare output is set to ~DIR when TCC counter matches CCn value |
| 1 | INVERTED | Compare output is set to DIR when TCC counter matches CCn value. |
Bits 16, 17, 18, 19 – POLn Channel n Polarity
Setting these bits enables the output polarity in single- and dual-slope PWM and dual-compare operations.
- These bits are not enable-protected
- These bits are write-synchronized. The WAVE Synchronization Busy bit of the Synchronization Busy register (SYNCBUSY.WAVE) must be checked to ensure that the WAVE.POLn synchronization is complete.
Channel n Polarity in Dual-Compare Mode
| Value | Name | Description |
|---|---|---|
| 0 | NORMAL | Compare output is initialized to ~DIR, set to DIR when TCC counter matches CCn value and set to ~DIR when TCC counter matches CC[n+WO_NUM/2] value. |
| 1 | INVERTED |
Compare output is initialized to DIR, set to ~DIR when TCC counter matches CCn value and set to DIR when TCC counter matches CC[n+WO_NUM/2] value. |
Bits 8, 9, 10, 11 – CICCENn Circular Compare/Capture Channel n Enable
- These bits are not enable-protected
- These bits are write-synchronized. The WAVE Synchronization Busy bit of the Synchronization Busy register (SYNCBUSY.WAVE) must be checked to ensure that the WAVE.CICCENn synchronization is complete.
Bit 7 – CIPEREN Circular Period Enable
Setting these bits enables the period circular buffer option. When the bit is set, the PER register value is copied back into the PERB register on an UPDATE condition.
- This bit is not enable-protected
- This bit is write-synchronized. The WAVE Synchronization Busy bit of the Synchronization Busy register (SYNCBUSY.WAVE) must be checked to ensure that the WAVE.CIPEREN synchronization is complete.
Bits 6:4 – RAMP[2:0] Ramp Operation
This bit field select Ramp operation (RAMP).
- This bit field is enable-protected
- This bit field is not synchronized
| Value | Name | Description |
|---|---|---|
| 0x0 | RAMP1 | RAMP1 operation |
| 0x1 | RAMP2A | Alternative RAMP2 operation |
| 0x2 | RAMP2 | RAMP2 operation |
| 0x3 | RAMP2C | Critical RAMP2 operation |
| Other | — | Reserved |
Bits 2:0 – WAVEGEN[2:0] Waveform Generation Operation
This bit field selects the waveform generation operation. The settings impact the top value and determine whether frequency or PWM frequency or PWM waveform generation should be used.
- This bit field is enable-protected
- This bit field is not synchronized
| Value | Name | Description |
|---|---|---|
| 0x0 | NFRQ | Normal Frequency |
| 0x1 | MFRQ | Match Frequency |
| 0x2 | NPWM | Normal PWM |
| 0x3 | DPWM | Dual Compare PWM |
| 0x4 | DSCRITICAL | Dual-slope PWM |
| 0x5 | DSBOTTOM | Dual-slope PWM |
| 0x6 | DSBOTH | Dual-slope PWM |
| 0x7 | DSTOP | Dual-slope PWM |
| Other | — | Reserved |