23.6.1 Control A

These bits are isused to select the capture or compare operation on channel x.

Writing a ‘1’ to CPTENn enables capture on channel x.

Writing a ‘0’ to CPTENn disables capture on channel x.

This bit enables the DMA One-shot Trigger Mode.

Writing a ‘1’ to this bit will generate a DMA trigger on the TCC cycle following a TCC_CTRLBSET_CMD_DMAOS command.

Writing a ‘0’ to this bit will generate DMA triggers on each TCC cycle.

Writing a ‘1’ to this bit will cause the TCC to wait for the end of the current cycle before evaluating the stop condition.

Writing a ‘0’ to this bit will make the TCC evaluate the stop condition immediately.

This bit field selects whether, on a retrigger event, the counter is cleared or reloaded on either the next GCLK_TCCn clock, or the next prescaled GCLK_TCCn clock. It is also possible to reset the prescaler on retrigger event.

This bit is used to keep the TCC running in Standby sleep mode.

This bit field select the Counter prescaler factor.

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit resets all registers in the TCC (except DBGCTRL) to their initial state, and the TCC will be disabled.

Writing a ‘1’ to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be discarded.

1. After CTRLA.SWRST is written to ‘1’, the user must poll the SYNCB.SWRST bit to verify when the reset operation is complete.
2. During a Software Reset, access to registers or bits not affected by a Software Reset are not allowed before the SYNCBUSY.SWRST bit is cleared by hardware.