14.3.11 DMA Channel x Clear Register

Name:	DMAxCLR
Offset:	0x2328, 0x2354, 0x2380, 0x23AC, 0x23D8, 0x2404, 0x2430, 0x245C


Bit	31	30	29	28	27	26	25	24
	CLR[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	CLR[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	CLR[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CLR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – CLR[31:0] Clear Register bits

Setting these bits high results in the corresponding data bit(s) from the DMABUF register being cleared. This action takes place after inverting and before setting, if applicable, and occurs prior to the data reaching their destination.