14.3.12 DMA Channel x Set Register

Name:	DMAxSET
Offset:	0x232C, 0x2358, 0x2384, 0x23B0, 0x23DC, 0x2408, 0x2434, 0x2460


Bit	31	30	29	28	27	26	25	24
	SET[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	SET[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	SET[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	SET[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – SET[31:0] Set Register bits

Setting these bits high results in the corresponding data bit(s) from the DMABUF register being set. This action takes place after clear and then inverting, if applicable, and occurs prior to the data reaching their destination.