4.3.4 Programmer’s Model

The programmer’s model for the dsPIC33A CPU is shown in Figure 4-2. All registers in the programmer’s model are memory-mapped and can be manipulated directly by instructions. Table 4-2 provides a description of each register in the programmer’s model.

In addition to the registers contained in the programmer’s model, the dsPIC33A devices contain control registers for Modulo Addressing, Bit-Reversed Addressing and Interrupts. These registers are described in subsequent sections of this document.

All registers associated with the programmer’s model are shown in Figure 4-2.

Table 4-2. Programmer's Model Register Descriptions
Register(s) NameDescription
W0 through W15(1)Working Register Array (Default Context)
W0 through W7(1,2)Working Register Array (Alternate Context 1-7)
ACCA,ACCB(1)72-bit DSP Accumulators (Context 0-7)
PC24-bit Program Counter
SR(1)ALU and DSP Engine Status Register
SPLIMStack Pointer Limit Value Register
RCOUNT32-bit REPEAT Loop Count Register (Context 0-7)
CORCONDSP Engine Configuration
Note:
  1. W0 through W15, ACCx and SR are not mapped to memory.
  2. W0 through W7 are part of Alternate W register sets.
Figure 4-2. dsPIC33A CPU Programmer’s Model