15.5.8 SUPC Backup Mode Register
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register (SYSC_WPMR).
This register is located in the VDDBU domain.
| Name: | SUPC_BMR |
| Offset: | 0x20 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| KEY[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BADXTWKEN | MRTCOUT | VBATREN | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VDD3V3SMWKEN | CORPORWKEN | FWUPEN | VBATWKEN | RTCWKEN | RTTWKEN | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 31:24 – KEY[7:0] Password Key
| Value | Name | Description |
|---|---|---|
| 0xA5 | PASSWD | Writing any other value in this field aborts the write operation. |
Bit 10 – BADXTWKEN Slow Crystal Oscillator Frequency Error Wake-up Enable
| Value | Description |
|---|---|
| 0 | A slow crystal oscillator frequency error does not wake up the system. |
| 1 | A slow crystal oscillator frequency error wakes up the system. |
Bit 9 – MRTCOUT RTCOUT0 Outputs Drive Mode
| Value | Name | Description |
|---|---|---|
| 0 | USERDEF | RTCOUT0 output is driven according to the configuration of the field RTC_MR.OUT0. |
| 1 | TAMP_OPT | In Backup mode, RTCOUT0 output is stuck at 1 while there is no tamper detection and driven according to the configuration of the field RTC_MR.OUT0 when a tamper is detected on a tamper input. |
Bit 8 – VBATREN Battery Voltage Event Report Enable
0 (DISABLE): Disables the report of event on VBAT voltage.
1 (ENABLE): Enables the report of event on VBAT voltage.
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | Disables the report of event on VBAT voltage. |
| 1 | ENABLE | Enables the report of event on VBAT voltage. |
Bit 6 – VDD3V3SMWKEN VDD3V3 Supply Monitor Wake-up Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | Wake-up on VDD3V3 supply monitor under voltage detection is disabled. |
| 1 | ENABLE | Wake-up on VDD3V3 supply monitor under voltage detection is enabled. |
Bit 5 – CORPORWKEN VDDCORE POR Wake-up Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | Wake-up on VDDCORE Power-On Reset Event is disabled. |
| 1 | ENABLE | Wake-up on VDDCORE Power-On Reset Event is enabled. |
Bit 4 – FWUPEN Force Wake-up Pin Wake-up Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | The FWUP pin has no wake-up effect. |
| 1 | ENABLE | The FWUP pin forces the wake-up of the core power supply. |
Bit 2 – VBATWKEN VBAT Supply Monitor Wake-up Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | Wake-up on VBAT supply monitor under voltage detection is disabled. |
| 1 | ENABLE | The RTC alarm signal forces the wake-up of the core power supply. |
Bit 1 – RTCWKEN Real-time Clock Wake-up Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | The RTC alarm signal has no wake-up effect. |
| 1 | ENABLE | The RTC alarm signal forces the wake-up of the core power supply. |
Bit 0 – RTTWKEN Real-time Timer Wake-up Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | The RTT alarm signal has no wake-up effect. |
| 1 | ENABLE | The RTT alarm signal forces the wake-up of the core power supply. |