15.5.6 SUPC Status Register
This register is located in the VDDBU domain.
| Name: | SUPC_SR |
| Offset: | 0x14 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RTCS | RTTS | FWKUPS | BADXTS | WKUPS | SXFME | SXFMS[1:0] | |||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| LPDBCS4 | LPDBCS3 | LPDBCS2 | LPDBCS1 | LPDBCS0 | |||||
| Access | R | R | R | R | R | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LCDS | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VDD3V3SMS | VDD3V3SMIS | VDD3V3SMRSTS | CORSMRSTS | VDD3V3SMWS | TDOSCSEL | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – RTCS RTC Wake-up Status (cleared by reading SUPC_WUSR)
| Value | Description |
|---|---|
| 0 | No wake-up due to the assertion of the RTC alarm has occurred since the last read of SUPC_WUSR. |
| 1 | At least one wake-up due to the assertion of the RTC alarm has occurred since the last read of SUPC_WUSR. |
Bit 30 – RTTS RTT Wake-up Status (cleared by reading SUPC_WUSR)
| Value | Description |
|---|---|
| 0 | No wake-up due to the assertion of the RTT alarm has occurred since the last read of SUPC_WUSR. |
| 1 | At least one wake-up due to the assertion of the RTT alarm has occurred since the last read of SUPC_WUSR. |
Bit 29 – FWKUPS FWUP Wake-up Status (cleared by reading SUPC_WUSR)
| Value | Description |
|---|---|
| 0 | No wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_WUSR. |
| 1 | At least one wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_WUSR. |
Bit 28 – BADXTS Slow Crystal Oscillator Wake-up Status (cleared by reading SUPC_WUSR)
| Value | Description |
|---|---|
| 0 | No wake-up due to slow crystal oscillator failure has occurred since the last read of SUPC_WUSR. |
| 1 | At least one wake-up due to slow crystal oscillator failure has occurred since the last read of SUPC_WUSR. |
Bit 27 – WKUPS WKUP Wake-up Status (cleared by reading SUPC_WUSR)
| Value | Description |
|---|---|
| 0 | No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_WUSR. |
| 1 | At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_WUSR. |
Bit 26 – SXFME Slow Crystal Oscillator Frequency Monitor Error (cleared on read)
| Value | Description |
|---|---|
| 0 | No error detected on slow crystal oscillator frequency since the last read of SUPC_SR. |
| 1 | At least one error (SXFMS=1 or 2) detected on slow crystal oscillator frequency since the last read of SUPC_SR. |
Bits 25:24 – SXFMS[1:0] Slow Crystal Oscillator Frequency Monitor Status (cleared on read)
| Value | Name | Description |
|---|---|---|
| 0 | GOOD | No frequency error detected. |
| 1 | FREQ_ERROR | The frequency has not been correct over 4 consecutive monitoring periods but there are still edges detected on the slow crystal oscillator output. |
| 2 | FAIL | No edge detected in the slow crystal oscillator output for at least 2 consecutive monitoring periods. |
Bits 16, 17, 18, 19, 20 – LPDBCSx Tamper Detection Wake-up Status (cleared by reading SUPC_ISR)
| Value | Description |
|---|---|
| 0 | No wake-up due to a tamper detection on WKUPx pin has occurred since the last read of SUPC_ISR. |
| 1 | At least one system wake-up due to a tamper detection on WKUPx pin has occurred since the last read of SUPC_ISR. |
Bit 8 – LCDS LCD Power Domain Status
| Value | Description |
|---|---|
| 0 | VDDLCD voltage is not supplied. |
| 1 | VDDLCD voltage is supplied. |
Bit 6 – VDD3V3SMS VDD3V3 Supply Monitor Output Status
| Value | Description |
|---|---|
| 0 | VDD3V3 supply monitor output reports a valid voltage. |
| 1 | VDD3V3 supply monitor output reports an invalid voltage. |
Bit 5 – VDD3V3SMIS VDD3V3 Supply Monitor Interrupt Status (cleared by reading SUPC_ISR)
| Value | Description |
|---|---|
| 0 | No VDD3V3 supply monitor under voltage detection since the last read of the SUPC_ISR. |
| 1 | At least one VDD3V3 supply monitor under voltage detection since the last read of the SUPC_ISR. |
Bit 4 – VDD3V3SMRSTS VDD3V3 Supply Monitor Reset Status (cleared by reading SUPC_WUSR)
| Value | Description |
|---|---|
| 0 | No VDD3V3 supply monitor detection has generated a VDDCORE reset since the last read of the SUPC_WUSR. |
| 1 | At least one VDD3V3 supply monitor detection has generated a VDDCORE reset since the last read of the SUPC_WUSR. |
Bit 3 – CORSMRSTS VDDCORE Supply Monitor Reset Status (cleared by reading SUPC_WUSR)
| Value | Description |
|---|---|
| 0 | No VDDCORE reset generated by VDDCORE POR event has been detected since the last read of the SUPC_WUSR. |
| 1 | A VDDCORE reset has been generated by VDDCORE POR event since the last read of the SUPC_WUSR. |
Bit 2 – VDD3V3SMWS VDD3V3 Supply Monitor Wake-up Status (cleared by reading SUPC_WUSR)
| Value | Description |
|---|---|
| 0 | No wake-up due to a VDD3V3 supply monitor event has occurred since the last read of SUPC_WUSR. |
| 1 | At least one wake-up due to a VDD3V3 supply monitor event has occurred since the last read of SUPC_WUSR |
Bit 0 – TDOSCSEL Timing Domain 32 kHz Oscillator Selection Status
| Value | Name | Description |
|---|---|---|
| 0 | RC | The timing domain slow clock (TD_SLCK) source is the slow RC oscillator output. |
| 1 | XTAL | The timing domain slow clock source is the 32.768 kHz crystal oscillator output. |