15.5.5 SUPC Wakeup Inputs Register

This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register (SYSC_WPMR).

This register is located in the VDDBU domain.

When the system is in Backup mode and VDD3V3 voltage is not supplied, only WKUP[2:0] pins can perform a wake-up.

Name: SUPC_WUIR
Offset: 0x10
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
  WKUPT14WKUPT13WKUPT12WKUPT11WKUPT10WKUPT9WKUPT8 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 2322212019181716 
 WKUPT7WKUPT6WKUPT5WKUPT4WKUPT3WKUPT2WKUPT1WKUPT0 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
  WKUPEN14WKUPEN13WKUPEN12WKUPEN11WKUPEN10WKUPEN9WKUPEN8 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 76543210 
 WKUPEN7WKUPEN6WKUPEN5WKUPEN4WKUPEN3WKUPEN2WKUPEN1WKUPEN0 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 – WKUPTx Wake-up Input Type x

ValueNameDescription
0 LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.
1 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the corresponding wake-up input forces the wake-up of the core power supply.

Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 – WKUPENx Wake-up Input Enable x

ValueDescription
0

The corresponding wake-up input has no wake-up effect.

1

The corresponding wake-up input is enabled for a wake-up of the core power supply.