15.5.10 SUPC Interrupt Enable Register
This register can only be written if the WPITEN bit is cleared in the System Controller Write Protection Mode register (SYSC_WPMR).
The following configuration values are valid for all listed bit names of this
register:
0: No effect.
1: Enables the corresponding interrupt.
| Name: | SUPC_IER |
| Offset: | 0x28 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | VBATSMEV | VDD3V3SMEV | |
| Access | | | | | | | W | W | |
| Reset | | | | | | | – | – | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | LPDBC4 | LPDBC3 | LPDBC2 | LPDBC1 | LPDBC0 | |
| Access | | | | W | W | W | W | W | |
| Reset | | | | – | – | – | – | – | |
Bit 17 – VBATSMEV VBAT Supply Monitor Event Interrupt Enable
The interrupt on VBAT
voltage event is enabled if SUPC_BMR.VBATREN=1.
Bit 16 – VDD3V3SMEV VDD3V3 Supply Monitor Event Interrupt
Enable
The VDD3V3 supply
monitor event occurs if SUPC_SMMR.VDD3V3SMSMPL > 0.
Bits 0, 1, 2, 3, 4 – LPDBCx WKUPx Pin Tamper Detection Interrupt Enable
