15.5.2 SUPC Supply Monitor Mode Register

This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register (SYSC_WPMR).

This register is located in the VDDBU domain.

Name: SUPC_SMMR
Offset: 0x04
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
   VDD3V3SMPWRMVDD3V3SMRSTEN VDD3V3SMSMPL[2:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 76543210 
     VDD3V3SMTH[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 13 – VDD3V3SMPWRM VDD3V3 Supply Monitor Power Supply Mode

ValueNameDescription
0 MANUAL The VDDBU power source selection is controlled by configuring the bit RSTC_MR.PWRSW.
1 AUTO_IOSM The VDDBU power source is VBAT when a VDD3V3 under voltage is detected by VDD3V3 Supply Monitor.

Bit 12 – VDD3V3SMRSTEN VDD3V3 Supply Monitor Reset Enable

ValueDescription
0

The VDDCORE reset is not asserted when a VDD3V3 supply monitor event occurs.
1

The VDDCORE reset is asserted when a VDD3V3 supply monitor event occurs.

Bits 10:8 – VDD3V3SMSMPL[2:0] VDD3V3 Supply Monitor Sampling Period

ValueNameDescription
0x0 DISABLED

VDD3V3 supply monitor is disabled
0x1 ALWAYS_ON

Continuous VDD3V3 supply monitoring
0x2 32SLCK VDD3V3 supply monitor is enabled for 1 period every 32 MD_SLCK periods

Energy optimization in Backup mode with VDD3V3 supplied.
0x3 256SLCK VDD3V3 supply monitor is enabled for 1 period every 256 MD_SLCK periods

Energy optimization in Backup mode with VDD3V3 supplied.
0x4 2048SLCK VDD3V3 supply monitor is enabled for 1 period every 2048 MD_SLCK periods

Energy optimization in Backup mode with VDD3V3 supplied.

Bits 3:0 – VDD3V3SMTH[3:0] VDD3V3 Supply Monitor Threshold

Selects the threshold voltage of the VDD3V3 supply monitor. Refer to the section “Electrical Characteristics” for voltage values.