15.5.7 SUPC Extended Mode Register

This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register (SYSC_WPMR).

This register is located in the VDDBU domain.

Name: SUPC_EMR
Offset: 0x1C
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
      COREBGENFULLGPBRCFLRSGPBR 
Access R/WR/WR/W 
Reset 000 
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
          
Access  
Reset  

Bit 18 – COREBGEN VDDCORE Voltage Regulator Bandgap Enable

ValueDescription
0

The bandgap of the VDDCORE internal voltage regulator is disabled.
1

The bandgap of the VDDCORE internal voltage regulator is enabled (mandatory when VDDCORE external voltage regulator is used).

Bit 17 – FULLGPBRC Full GPBR Clean

ValueDescription
0

When a GPBR clear is asserted, half GPBR registers are cleared.
1

When a GPBR clear occurs, GPBR registers are all cleared.

Bit 16 – FLRSGPBR Flash Erase GPBR

ValueDescription
0

When a Flash Erase occurs, there is no action on GPBR registers.
1

When a Flash Erase occurs, GPBR registers are cleared.