15.5.9 SUPC Wakeup Status Register
This register is located in the VDDBU domain.
| Name: | SUPC_WUSR |
| Offset: | 0x24 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WKUPIS15 | WKUPIS14 | WKUPIS13 | WKUPIS12 | WKUPIS11 | WKUPIS10 | WKUPIS9 | WKUPIS8 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WKUPIS7 | WKUPIS6 | WKUPIS5 | WKUPIS4 | WKUPIS3 | WKUPIS2 | WKUPIS1 | WKUPIS0 | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| VDD3V3SMRSTS | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RTCS | RTTS | VDD3V3SMWS | FWUPS | BADXTWKS | WKUPS | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – WKUPISx WKUPx Input Wake-up Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No wake-up due to the assertion of the WKUPx pin has occurred since the last read of SUPC_WUSR. |
| 1 | At least one wake-up due to the assertion of the WKUPx pin has occurred since the last read of SUPC_WUSR. |
Bit 8 – VDD3V3SMRSTS VDD3V3 Supply Monitor Reset Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No VDDCORE reset due to VDD3V3 supply monitor event since the last read of the SUPC_WUSR. |
| 1 | VDDCORE reset due to VDD3V3 supply monitor event since the last read of the SUPC_WUSR. |
Bit 5 – RTCS RTC Wake-up Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No wake-up due to the assertion of the RTC alarm has occurred since the last read of SUPC_WUSR. |
| 1 | At least one wake-up due to the assertion of the RTC alarm has occurred since the last read of SUPC_WUSR. |
Bit 4 – RTTS RTT Wake-up Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No wake-up due to the assertion of the RTT alarm has occurred since the last read of SUPC_WUSR. |
| 1 | At least one wake-up due to the assertion of the RTT alarm has occurred since the last read of SUPC_WUSR. |
Bit 3 – VDD3V3SMWS VDD3V3 Supply Monitor Wake-up Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No wake-up due to VDD3V3 supply monitor event has occurred since the last read of SUPC_WUSR. |
| 1 | At least one wake-up due to VDD3V3 supply monitor event has occurred since the last read of SUPC_WUSR. |
Bit 2 – FWUPS FWUP Wake-up Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_WUSR. |
| 1 | At least one wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_WUSR. |
Bit 1 – BADXTWKS Slow Crystal Oscillator Frequency Error Wake-up Status (cleared on read)
| Value | Description |
|---|---|
| 0 | No wake-up due to slow crystal oscillator frequency error has occurred since the last read of SUPC_WUSR. |
| 1 | At least one wake-up due to slow crystal oscillator frequency error has occurred since the last read of SUPC_WUSR. |
Bit 0 – WKUPS WKUP Wake-up Status (cleared on read)
In case the wake-up is issued from tamper detection circuitry (SUPC_WUMR.LPDBCENx=1), the SUPC_SR.LPDBCSx flags report the input(s) that triggered the wake-up.
| Value | Description |
|---|---|
| 0 | No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_WUSR. |
| 1 | At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_WUSR. |