15.5.4 SUPC Wakeup Mode Register
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register (SYSC_WPMR).
This register is located in the VDDBU domain.
| Name: | SUPC_WUMR |
| Offset: | 0x0C |
| Reset: | 0x0000_000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| LPDBC4[2:0] | LPDBC3[2:0] | LPDBC2[2] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| LPDBC2[1:0] | LPDBC1[2:0] | LPDBC0[2:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WKUPDBC[2:0] | FWUPDBC[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LPDBCEN4 | LPDBCEN3 | LPDBCEN2 | LPDBCEN1 | LPDBCEN0 | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | _ | 0 | 0 | 0 | 0 |
Bits 16:18, 19:21, 22:24, 25:27, 28:30 – LPDBCx Low-power Debouncer Period of WKUPx
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | Disables the low-power debouncers. |
| 1 | 2_RTCOUT | WKUPx in active state for at least 2 RTCOUTx clock periods |
| 2 | 3_RTCOUT | WKUPx in active state for at least 3 RTCOUTx clock periods |
| 3 | 4_RTCOUT | WKUPx in active state for at least 4 RTCOUTx clock periods |
| 4 | 5_RTCOUT | WKUPx in active state for at least 5 RTCOUTx clock periods |
| 5 | 6_RTCOUT | WKUPx in active state for at least 6 RTCOUTx clock periods |
| 6 | 7_RTCOUT | WKUPx in active state for at least 7 RTCOUTx clock periods |
| 7 | 8_RTCOUT | WKUPx in active state for at least 8 RTCOUTx clock periods |
Bits 14:12 – WKUPDBC[2:0] Wake-up Inputs Debouncer Period
| Value | Name | Description |
|---|---|---|
| 0 | IMMEDIATE | Immediate, no debouncing, detected active at least on one Slow Clock edge. |
| 1 | 3_SK | WKUPx shall be in its active state for at least 3 MD_SLCK periods |
| 2 | 32_SK | WKUPx shall be in its active state for at least 32 MD_SLCK periods |
| 3 | 512_SK | WKUPx shall be in its active state for at least 512 MD_SLCK periods |
| 4 | 4096_SK | WKUPx shall be in its active state for at least 4,096 MD_SLCK periods |
| 5 | 32768_SK | WKUPx shall be in its active state for at least 32,768 MD_SLCK periods |
Bits 10:8 – FWUPDBC[2:0] Force Wake-up Inputs Debouncer Period
| Value | Name | Description |
|---|---|---|
| 0 | IMMEDIATE | Immediate, no debouncing, detected active at least on one Slow Clock edge. |
| 1 | 3_SK | WKUPx shall be in its active state for at least 3 MD_SLCK periods |
| 2 | 32_SK | WKUPx shall be in its active state for at least 32 MD_SLCK periods |
| 3 | 512_SK | WKUPx shall be in its active state for at least 512 MD_SLCK periods |
| 4 | 4096_SK | WKUPx shall be in its active state for at least 4,096 MD_SLCK periods |
| 5 | 32768_SK | WKUPx shall be in its active state for at least 32,768 MD_SLCK periods |
Bits 0, 1, 2, 3, 4 – LPDBCENx Tamper Enable for WKUPx Pin
| Value | Description |
|---|---|
| 0 | The WKUPx input pin is not used as a tamper pin. It can be used as a wake-up pin by writing SUPC_WUIR.WKUPENx=1. |
| 1 | The WKUPx input pin acts as a tamper pin and a tamper event forces a system wake-up. |