15.5.3 SUPC Mode Register
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode register (SYSC_WPMR).
| Name: | SUPC_MR |
| Offset: | 0x08 |
| Reset: | 0x00005000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| KEY[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| OSCBYPASS | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| IO_BACKUP_ISO | CORSMDIS | CORSMRSTEN | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 1 | 0 | 1 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| VREGDIS | CORSMM | LCDMODE[1:0] | LCDOUT[3:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:24 – KEY[7:0] Password Key
| Value | Name | Description |
|---|---|---|
| 0xA5 | PASSWD | Writing any other value in this field aborts the write operation. |
| 0x59 | PASSWD1 | Modifies the VREGDIS bit. Other bits are not affected. |
Bit 20 – OSCBYPASS Slow Crystal Oscillator Bypass
| Value | Name | Description |
|---|---|---|
| 0 | NO_EFFECT | No effect. Clock selection depends on the value of the bit SUPC_CR.TDXTALSEL. |
| 1 | BYPASS | The slow crystal oscillator is bypassed if SUPC_CR.TDXTALSEL=1. The bit OSCBYPASS must be set prior to setting the bit TDXTALSEL. |
Bit 14 – IO_BACKUP_ISO Backup Domain IO Isolation Control
| Value | Description |
|---|---|
| 0 | Isolation mode is enabled. |
| 1 | Isolation mode is disabled. |
Bit 13 – CORSMDIS VDDCORE Supply Monitor Disable
| Value | Description |
|---|---|
| 0 | The VDDCORE supply monitor is enabled. |
| 1 | The VDDCORE supply monitor is disabled. |
Bit 12 – CORSMRSTEN VDDCORE Supply Monitor Reset Enable
| Value | Description |
|---|---|
| 0 | The VDDCORE domain reset signal is not asserted when a VDDCORE supply monitor under-voltage detection occurs. |
| 1 | The VDDCORE domain reset signal is asserted when a VDDCORE supply monitor under-voltage detection occurs. |
Bit 7 – VREGDIS Internal VDDCORE Voltage Regulator Disable
To write this bit, SUPC_MR.KEY must be set to 0x59.
This bit is located in the VDDBU domain.
| Value | Name | Description |
|---|---|---|
| 0 | INT_VREG | Internal VDDCORE voltage regulator is enabled. |
| 1 | EXT_VREG | Internal VDDCORE voltage regulator is disabled (external power supply is used). |
Bit 6 – CORSMM VDDCORE Supply Monitor Output Mode
| Value | Name | Description |
|---|---|---|
| 0 | NO_EFFECT | VDDCORE supply monitor output value has no effect. Power-on is performed whatever the value of the supply monitor output. |
| 1 | VALID_VDD | VDDCORE supply monitor output value is checked to validate the VDDCORE domain power-on. |
Bits 5:4 – LCDMODE[1:0] LCD Controller Mode of Operation
| Value | Name | Description |
|---|---|---|
| 0x0 | LCDOFF | The internal supply source and the external supply source are both deselected (OFF Mode). |
| 0x2 | LCDON_EXTVR | The external supply source for LCD (VDDLCD) is selected (the embedded LCD voltage regulator is in High-impedance mode). |
| 0x3 | LCDON_INVR | The internal voltage regulator for VDDLCD is selected (Active mode). |
Bits 3:0 – LCDOUT[3:0] LCD Voltage Regulator Output
Adjusts the output voltage of the embedded LCD Voltage Regulator. Refer to the section “Electrical Characteristics” for voltage values.