15.5.1 SUPC Control Register
This register can only be written if the WPEN bit is cleared in the System Controller Write Protection Mode Register (SYSC_WPMR).
| Name: | SUPC_CR |
| Offset: | 0x00 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| KEY[7:0] | |||||||||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TDXTALSEL | VROFF | SHDWEOF | SHDW | ||||||
| Access | W | W | W | W | |||||
| Reset | – | – | – | – |
Bits 31:24 – KEY[7:0] Password
| Value | Name | Description |
|---|---|---|
| 0xA5 | PASSWD | Writing any other value in this field aborts the write operation. |
Bit 3 – TDXTALSEL Timing Domain Clock on Slow Crystal Oscillator
| Value | Name | Description |
|---|---|---|
| 0 | NO_EFFECT | No effect. |
| 1 | XTAL32K | If KEY=0xA5, TDXTALSEL switches the slow clock of the timing domain (TD_SLCK) on the 32.768 kHz crystal oscillator output. |
Bit 2 – VROFF Voltage Regulator Off
| Value | Name | Description |
|---|---|---|
| 0 | NO_EFFECT | No effect. |
| 1 | STOP_VREG | If KEY=0xA5, VROFF asserts the VDDCORE domain reset and stops the voltage regulator. |
Bit 1 – SHDWEOF Shutdown End Of Frame
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | If KEY=0xA5, activates the Shutdown pin once the end of frame of the LCD driver occurs. |
Bit 0 – SHDW Shutdown
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | If KEY=0xA5, activates the Shutdown pin. |