2.9.4 Configuring the DDR4 Subsystem

General

The following figure shows the General tab.

As shown in the preceding figure, the General tab provides the following options.

• Top
  • Protocol: By default, this is set to DDR4.
  • Generate PHY only: Enable this option to create a PHY-only DDR4 subsystem.
• Clock: To set the DDR4 memory clock frequency and user logic clock rate. The user clock frequency is automatically populated.
  • Memory Clock Frequency (MHz): By default, the clock frequency is set to 800 MHz. The value must be within 0–800 MHz
  • CCC PLL Clock Multiplier: Valid range is 1–49
  • CCC PLL Reference Clock Frequency (MHz) : Depends upon Memory Clock Frequency (MHz) and CCC PLL Clock Multiplier. The value is 200 MHz when memory frequency is 800 MHz and clock multiplier is 4.
  • User Logic Clock Rate: QUAD
  • User Clock Frequency: Depends upon Memory Clock Frequency (MHz) and CCC PLL Clock Multiplier. The value is 200 MHz when memory frequency is 800 MHz and clock multiplier is 4.
  • CK/CA additive offset: The value must be within 0–7. The default value is 4.
• Topology: To set the topology of the memory system, including the address bits, bank configurations, DM modes, and ECC.
  • Memory Format: COMPONENT or type of DIMM (UDIMM, RDIMM, LRDIMM, or SODIMM)
  • DQ Width: 16-bit, 32-bit, or 64-bit
    Important: AXI width must be larger than the data width and clock rate.
  • SDRAM Number of Ranks: 1
  • Enable Address mirroring on odd ranks: Disabled
  • DQ/DQS group size: 8
  • Row Address width: The value must be within [13, 17] range
  • Column Address Width: 10
  • Bank Address width: 2
  • Bank Group Address width: The value must be within [1, 2] range
  • Enable DM: OFF or DM (enabled)
  • Enable Parity/Alert: When the memory format is RDIMM or LRDIMM, this option can be selected to support the Alert signal from DDR memory when it detects a CA parity error.
  • Enable ECC: Check box toggle option
  • Number of clock outputs: 1

Memory Initialization

The following figure shows the Memory Initialization tab.

As shown in the preceding figure, the Memory Initialization tab provides the following options.

Memory Timing

The following figure shows the Memory Timing tab.

As shown in the preceding figure, the Memory Timing options provides the following options.

Controller

The following figure shows the Controller tab.

As shown in the preceding figure, the Controller tab provides the following options.

• Instance Select: Enables the option to select the DDR4 subsystem instance number that is used to unify the controller instance. PolarFire family supports a maximum of six DDR4 subsystem instances.
  • Instance Number:
• User Interface
  • Fabric Interface: options are AMBA AXI3/4 and native interface. The following table lists the supported AXI bus data widths with respect to the DQ widths.

  • Table 2-32. Supported AXI Bus Data Width

    DQ Width	Supported AXI Data Bus Width
    x16	64, 128
    x32	64, 128, 256
    x64	512

    Data Bus Turnaround—provides additional bus turnaround time between different SDRAM ranks. The turnaround time is the number of clock cycles it takes to change the access from one rank to another rank for back-to-back memory accesses (read to read, read to write, write to write, and write to read). The AXI interface address is mapped based on the type of the Address Ordering selected in the PF_DDR4 configurator. For example, if Chip-Row-Bank-Col is selected, and if a row address width and column address width is configured for 13 and 11, the AXI address is mapped as shown in the following table.

  • Table 2-33. AXI Address Mapping

    AXI Address	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
    Column Address																				C10	C9	C8	C7	C6	C5	C4	C3	C2	C1	C0
    Bank Address																	BA2	BA1	BA0
    Row Address				R12	R11	R10	R9	R8	R7	R6	R5	R4	R3	R2	R1	R0

    Important: The address mapping shown in the preceding table is applicable to Native interface also.
  • AXI Width: 64, 128, 256, or 512
  • AXI ID Width: Valid range is 1–8
• Efficiency: Provides control over memory refresh, precharge, and address ordering options.
  • Enable Activate/Precharge look-head: Check box toggle option
  • Number of Banks to lookup: 4, 8, or 16
  • Address Ordering: Any one of the following options can be selected:
    • Chip-Row-BG-Bank-Col
    • Chip-BG-Bank-Row-Col
    • Chip-Row-BG1-Bank-Col-BG0
      Important: Number of banks to lookup must be 8 or 16 when address ordering is set to Chip-Row-BG1-Bank-Col-BG0.
• ODT Activation Setting on Write: provides options to enable ODT on write operations.
  • Enable Rank0 - ODT0: Enabled by default. Can Disabled or enabled.
  • Enable Rank0 - ODT1: Not supported
  • Enable Rank1 - ODT0: Not supported
  • Enable Rank1 - ODT1: Enabled (fixed).
• Low Power
  • Enable self request refresh control: When selected, this option saves power
• Misc
  • Enable RE-INIT Controls: When selected, the configurator exposes the CTRLR_INIT signal. The initialization begins when this signal is asserted high for minimum 4 clock cycles in the fabric clock domain.

DDR4 Additional Controller Options

For DDR4, the Controller tab includes the following additional settings under Efficiency.

• The Address Ordering includes the additional setting Chip-Row-BG1-Bank-Col-BG0.

  This selection will map the LSBs of an address to the BG0 field of the memory. This results in alternating Bank Groups during a burst operation based on the tCCD_S timing parameter (see memory device datasheet for tCCD_S settings). The tCCD_S parameter is the timing parameter which results in a better efficient operation for the DDR IP Configurator in the DDR4 mode.

  

• The Number of banks to look up option includes additional selections for 8 and 16. The default selection is 4.

  This must be set to the number of banks in a Bank Group of the DDR4 memory device being used. Selecting a higher value is more challenging in terms if timing closure on the controller. A setting of 8 works for all but the most congested designs. A setting of 16 works for designs that have 15% timing margin or more.

  

Miscellaneous

The following figure shows the Misc. tab.

As shown in the preceding figure, the Misc. options provides the following options.

• Simulation Options
  • Simulation mode:
    • Fast (skip training and settling time): In this mode, the DDR4 subsystem skips the DDR4 training sequence and asserts CTRLR_READY without waiting for the settling time. CTRLR_READY is asserted within 8 μs.
    • Training (skip settling time): In this mode, the DDR4 subsystem performs the DDR4 training sequence but asserts CTRLR_READY without waiting for settling time. CTRLR_READY is asserted within 240 μs.
    • Full (training and settling time): In this mode, the DDR4 subsystem performs the DDR4 training sequence and also waits for settling time before asserting CTRLR_READY. In this mode, CTRLR_READY is asserted within 10 ms.
• Throughput Options
  • Pipe Lining: Adds pipeline registers to Training IP (TIP) write and read data path to improve static timing closure.