2.9.3 Configuring the LPDDR3 Subsystem

General

The following figure shows the General tab.

As shown in the preceding figure, the General tab provides the following options.

• Top
  • Protocol: By default, this is set to LPDDR3.
  • Generate PHY only: Enable this option to create a PHY-only LPDDR3 subsystem.
• Clock: To set the LPDDR3 memory clock frequency and user logic clock rate. The user clock frequency is automatically populated.
  • Memory Clock Frequency (MHz): Valid range is 400–667 MHz
  • CCC PLL Clock Multiplier: Valid range 1 to 49
  • CCC PLL Reference Clock Frequency (MHz): Depends on the setting of CCC PLL Clock Multiplier.
  • User Logic Clock Rate: QUAD
  • User Clock Frequency: 166.5 MHz
  • CK/CA additive offset: The value must be within 0–7. The default value is 4.
• Topology: To set the topology of the memory system, including the address bits, bank configurations, DM modes, and ECC.
  • Memory Format: COMPONENT
  • DQ Width: Select any one of the following options:
    • 16
    • 32
  • SDRAM Number of Ranks: 1
  • DQ/DQS group size: 8
  • Row Address width: The value must be within [14, 15] range
  • Column Address Width: The value must be within [10, 12] range
  • Bank Address width: 3
  • Enable DM: Select any one of the following options:
    • OFF
    • DM
  • Number of clock outputs: 1

Memory Initialization

The following figure shows the Memory Initialization tab.

As shown in the preceding figure, the Memory Initialization tab provides the following options.

• Mode Register 2
  • Data Latency (#RL, #WL): Select any one of the following options:
    • (6, 3)
    • (8, 4)
    • (9, 5)
    • (10, 6)
    • (11, 6)
    • (12, 6)
  By Default, (10, 6) is selected.
• Mode Register 3
  • Output Drive Strength: Select any one of the following options:
    • 34.3 typical pull-down/pull-up
    • 40 typical pull-down/pull-up
    • 48 typical pull-down/pull-up
    • 34.3 typical pull-down, 40 typical pull-up
    • 40 typical pull-down, 48 typical pull-up
    • 34.3 typical pull-down, 48 typical pull-up
• Mode Register 11
  • DQ ODT: Select any one of the following options:
    • Disable
    • RZQ/4
    • RZQ/2
    • RZQ/1
  • Power down ODT: Disabled or Enabled

Memory Timing

The following figure shows the Memory Timing tab.

Controller

The following figure shows the Controller tab.

As shown in the preceding figure, the Controller tab provides the following options.

• Instance Select: Enables the option to select of the LPDDR3 subsystem instance number that is used to unify the controller instance. PolarFire family supports a maximum of six LPDDR3 subsystem instances.
  • Instance Number:
• User Interface
  • Fabric Interface: Options are AMBA AXI3/4 and native interface. The following table lists the supported AXI bus data widths with respect to the DQ widths.

  • Table 2-30. Supported AXI Bus Data Width

    DQ Width	Supported AXI Data Bus Width
    x16	64, 128
    x32	64, 128, 256
    x64	512

    Data Bus Turnaround—provides additional bus turnaround time between different SDRAM ranks. The turnaround time is the number of clock cycles it takes to change the access from one rank to another rank for back-to-back memory accesses (read to read, read to write, write to write, and write to read). The AXI interface address is mapped based on the type of the Address Ordering selected in the PF_LPDDR3 configurator. For example, if Chip-Row-Bank-Col is selected, and if a row address width and column address width is configured for 13 and 11, the AXI address is mapped as shown in the following table.

  • Table 2-31. AXI Address Mapping

    AXI Address	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
    Column Address																				C10	C9	C8	C7	C6	C5	C4	C3	C2	C1	C0
    Bank Address																	BA2	BA1	BA0
    Row Address				R12	R11	R10	R9	R8	R7	R6	R5	R4	R3	R2	R1	R0

    Important: The address mapping shown in the preceding table is applicable to Native interface also.
  • AXI Width: 64, 128, or 256
  • AXI ID Width: Valid range is 1–8
• Efficiency: Provides control over memory refresh, precharge, and address ordering options.
  • Enable Activate/Precharge look-head: Check box toggle option
  • Enable User Refresh Controls: Check box toggle option
  • Address Ordering: Any one of the following options is supported:
    • Chip-Bank-Row-Col
    • Chip-Row-Bank-Col
• Misc
  • Enable RE-INIT Controls: When selected, the configurator exposes the CTRLR_INIT signal. The initialization begins when this signal is asserted high for minimum 4 clock cycles in the fabric clock domain.
• ODT Activation Setting on Write: Provides options to enable ODT on write operations.
  • Enable Rank0 - ODT0: Supported
  • Enable Rank0 - ODT1: Not supported
  • Enable Rank1 - ODT0: Not supported
  • Enable Rank1 - ODT1: Not supported
• Low Power
  • Enable self request refresh control: Use this option to save power.

Miscellaneous

The Misc. tab provides the following options.

As shown in the preceding figure, the Misc. tab provides the following options.

• Simulation Options
  • Simulation mode:
    • Fast (skip training and settling time): In this mode, the LPDDR3 subsystem skips the LPDDR3 training sequence and asserts CTRLR_READY without waiting for the settling time. CTRLR_READY is asserted within 8 μs.
    • Training (skip settling time): In this mode, the LPDDR3 subsystem performs the LPDDR3 training sequence but asserts CTRLR_READY without waiting for settling time. CTRLR_READY is asserted within 240 μs.
    • Full (training and settling time): In this mode, the LPDDR3 subsystem performs the LPDDR3 training sequence and also waits for settling time before asserting CTRLR_READY. In this mode, CTRLR_READY is asserted within 10 ms.
• Throughput Options
  • Pipe Lining: Adds pipeline registers to Training IP (TIP) write and read data path to improve static timing closure.