17.5.14.1.4 DLL-Off Mode (DDR3)

DLL-off mode enables DDR3 SDRAMs to be operated at low frequencies. The UDDRC supports DLL-off mode, and transitions between DLL-on and DLL-off mode, under software control.

To enable DLL-off mode from initialization, the following register fields must be set:

• INIT3.emr[0], so that the SDRAM mode register is set for DLL-off mode
• MSTR.dll_off_mode = 1
• The DDR PHY should be put in PLL-bypass mode

To perform a transition between DLL-off and DLL-on modes, the software must implement the sequence specified in the JEDEC specification.