17.5.14.1.3 Assertion of dfi_dram_clk_disable

Assertion of dfi_dram_clk_disable occurs only if PWRTL.en_dfi_dram_clk_disable = 1.

dfi_dram_clk_disable is also dependent on the operating mode:

• In DDR2/DDR3, dfi_dram_clk_disable can be asserted only in Self-refresh mode.
• In LPDDR2/LPDDR3, dfi_dram_clk_disable can be asserted in the following modes:
  • in Self-refresh
  • in Power-down
  • in Deep Power-down
  • in Normal mode (“Clock Stop” feature)

The timing of the assertion and de-assertion of dfi_dram_clk_disable in various modes is as follows:

• In Self-refresh or Self-refresh Power-down mode:
  • Asserted at least DFITMG0.dfi_t_ctrl_delay + DRAMTMG5.t_cksre DFITMG1.dfi_t_dram_clk_disable cycles after SRE command.
  • De-asserted at least DFITMG1.dfi_t_dram_clk_enable + DRAMTMG5.t_cksrx - DFITMG0.dfi_t_ctrl_delay cycles before SRX command.
• In Power-down:
  • Asserted at least DFITMG0.dfi_t_ctrl_delay + DRAMTMG7.t_ckpde -DFITMG1.dfi_t_dram_clk_disable cycles after PDE command.
  • De-asserted at least DFITMG1.dfi_t_dram_clk_enable + DRAMTMG7.t_ckpdx -DFITMG0.dfi_t_ctrl_delay cycles before PDX command.
• In Deep Power-down:
  • Asserted at least DFITMG0.dfi_t_ctrl_delay + DRAMTMG6.t_ckdpde - DFITMG1.dfi_t_dram_clk_disable cycles after DPDE command.
  • De-asserted at least DFITMG1.dfi_t_dram_clk_enable + DRAMTMG6.t_ckdpdx -DFITMG0.dfi_t_ctrl_delay cycles before DPDX command.
• In Normal mode (Clock Stop):
  • Asserted at least DFITMG0.dfi_t_ctrl_delay - DFITMG0.dfi_t_dram_clk_disable cycles after any command other than SRE/PDE/DPDE.
  • De-asserted at least DFITMG1.dfi_t_dram_clk_enable + DRAMTMG6.t_ckcsx - DFITMG0.dfi_t_ctrl_delay cycles before any command other than SRX/PDX/DPDX.

For more information about the above modes, see Register Descriptions.