17.5.14.1.1 Precharge Power-down

Entering Precharge Power-down

When PWRCTL.powerdown_en = 1 (see Register Descriptions), UDDRC automatically enters precharge power-down when the period specified by PWRTMG.powerdown_to_x32 has passed while the UDDRC is idle (except for issuing refreshes).

Entering Precharge Power-down mode involves the following steps:

  1. If there is a self-refresh exit previously, wait for at least one refresh command (or 8 per-bank refresh commands if LPDDR2/3 per-bank refresh is enabled) to all active ranks. Auto-refresh logic must be enabled, or refresh should be issued using direct software requests of refresh command through DBGCMD.rank*_refresh.
  2. Precharging (closing) all open pages. Pages are closed one-at-a-time in no specified order.
  3. Waiting for tRP (row precharge) idle period.
  4. Issuing the command to enter precharge power-down (NOP/deselect with CKE = 0).
  5. This step occurs only if DFI low-power interface for power-down is enabled (DFILPCFG0.dfi_lp_en_pd). Attempts an entry to Low-power mode through DFI low-power interface and with dfi_lp_wakeup set by DFILPCFG0.dfi_lp_wakeup_pd. The low power entry attempt is delayed with DFITMG0.dfi_t_ctrl_delay + DRAMTMG7.t_ckpde clock cycles. This is needed to satisfy SDRAM timings related to disabling clocks when the PHY is programmed to gate the clock to save maximum power.

If the UDDRC receives a read or write request from the SoC core during step 2 or step 3 above, the power-down entry is immediately aborted. The same is true if PWRCTL.powerdown_en is driven to ‘0’ during step 2 or step 3. Once the power-down entry command is issued, then proper power-down exit is required, as described in “Entering Precharge Power-down” below.

Exiting Precharge Power-down

Once the UDDRC has put the DDR SDRAM device(s) in Precharge Power-down mode, the UDDRC automatically performs the precharge power-down exit sequence for any of the following reasons:

  • A refresh cycle is required to any rank in the system.
  • The UDDRC receives a new request from the SoC core.
  • A self-refresh entry is requested.
  • PWRCTL.powerdown_en is set to 0 (see Register Descriptions).

The UDDRC follows these steps when exiting Precharge Power-down mode:

  1. Inserting any NOP/deselect commands required to satisfy the tCKE requirement after entering precharge power-down.
  2. This step occurs only if DFI Low-power mode entry during power-down entry is successful. Performs an exit from DFI Low-power mode. DFI Low-power mode is exited after the wakeup time specified by DFILPCFG0.dfi_lp_wakeup_pd, but not earlier than DFITMG1.dfi_t_dram_clk_enable + DRAMTMG6.t_ckpdx clock cycles.
  3. Issuing the power-down exit command (NOP/deselect with CKE = 1).
  4. Issuing NOP/deselect for the period defined by tXP.
Note:
  1. DDR2: Fast Exit versus Slow Exit Active Power-down
The DDR2 Specification describes two different variations on active power-down exit, depending on the programmed value of MR bit 12. As the UDDRC uses precharge power-down rather than active power-down, this programming has no effect on the UDDRC or th SDRAM devices.
  2. DDR3: Fast Exit versus Slow Exit Precharge Power-down
The DDR3 Specification describes two different variations on precharge power-down exit, depending on the programmed value of MR0 bit 12. If slow precharge power-down is used (MR0[12] = 0), DRAMTMG1.t_xp should be set to tXPDLL. If fast precharge power-down is used (MR0[12] = 1), DRAMTMG1.t_xp should be set to tXP.
  3. Other supported DDR protocols do not specify the difference between fast and slow power-down exit.