17.5.14.1.2 Deep Power-Down

This power saving mode is applicable for LPDDR2 and LPDDR3 devices only.

Entering Deep Power-down

By setting the PWRCTL.deeppowerdown_en bit (see Register Descriptions), you can put the SDRAM device(s) into Deep Power-down mode, if all the following conditions are true:

  • The period specified by PWRTMG.powerdown_to_x32 has passed while the UDDRC is idle (except for issuing refreshes).
  • PWRCTL.selfref_sw = 0
  • PWRCTL.selfref_en = 0
  • If HWLPCTL.hw_lp_en = 1, DPD is entered only when the hardware low-power interface has completed a self-refresh exit. (This can be checked by observing STAT.operating_mode and STAT.selfref_type).
  • If HWLPCTL.hw_lp_exit_idle_en = 1, DPD is entered only when all bits of cactive_in_ddrc = 0

Entering Deep power-down involves the following steps:

  1. If there is a self-refresh exit previously, wait for at least one refresh command (or 8 per-bank refresh commands if LPDDR2/3 per-bank refresh is enabled) to all active ranks. Auto-refresh logic must be enabled, or refresh should be issued using direct software requests of refresh command through DBGCMD.rank*_refresh.
  2. Precharging (closing) all open pages. Pages are closed one-at-a-time in no specified order.
  3. Waiting for tRP (row precharge) idle period.
  4. Issuing the command to enter deep power-down. For multi-rank systems, all chip-selects are asserted so that all ranks enter deep power-down simultaneously. The deep power-down entry command is:

    CKE = 0, CSN = 0, CA0 = 1, CA1 = 1, CA2 = 0

  5. This step occurs only if DFI low-power interface for deep power-down is enabled (DFILPCFG0.dfi_lp_en_dpd). It attempts an entry to Low-power mode through DFI low-power interface with dfi_lp_wakeup set by DFILPCFG0.dfi_lp_wakeup_dpd. The low power entry attempt is delayed with DFITMG0.dfi_t_ctrl_delay + DRAMTMG6.t_ckdpde clock cycles, this is needed to satisfy SDRAM timings related to disabling clocks when the PHY is programmed to gate the clock, to save maximum power.

If the UDDRC receives a read or write request from the SoC core during step 1 or step 3 above, the deep power-down entry is immediately aborted. The same is true if PWRCTL.deep_powerdown_en is driven to ‘0’ during step 1 or step 3. Once the deep power-down entry command is issued, proper deep power-down exit is required, as described in the following section.

Note: Contents of SDRAM may be lost upon entry into Deep Power-down mode.

Exiting Deep Power-down

Once the UDDRC puts the DDR SDRAM device(s) in Deep Power-down mode, the UDDRC automatically exits deep power-down and re-runs the initialization sequence when PWRCTL.deeppowerdown_en is reset to 0 (see Register Descriptions). An exit from DFI Low-power mode is performed prior to exiting deep power-down (this occurs only if DFI Low- power mode entry during deep power-down entry is successful). DFI Low-power mode is exited after the wakeup time specified by DFILPCFG0.dfi_lp_wakeup_dpd, but not earlier than DFITMG1.dfi_t_dram_clk_enable + DRAMTMG6.t_ckdpdx clock cycles.

Exiting Deep power-down involves the following steps when SDRAM initialization is performed by the PHY (INIT0.skip_dram_init = 2’b01 or 2’b11):

  1. To prevent the UDDRC asserting dfi_cke before the SDRAM initialization is complete, it is necessary to set INIT0.skip_dram_init = 2’b11 before clearing PWRCTL.deeppowerdown_en.
  2. If step 1 is performed, to ensure that controller updates will not occur when INIT0.skip_dram_init will be changed back to 2’b01 (which could make DFI bus active when dfi_ctrlupd_req), it is necessary to set DFIUPD0.dis_auto_ctrlupd and DBG1.dis_hif and to stop sending software controller updates before clearing PWRCTL.deeppowerdown_en.
  3. Clear DFIMISC.dfi_init_complete_en=“0” register, before clearing PWRCTL.deeppowerdown_en to ensure that the UDDRC will wait until the PHY completes its initialization.
  4. Reset PWRCTL.deeppowerdown_en to 0 and poll STAT.operating mode to detect when the UDDRC exits from DPD and then start the SDRAM initialization by setting the PUB_PIR register.
  5. Once PHY Init is started and PIR is programmed, set back the old value of skip_dram_init, if it was updated as described in step 1.
  6. Poll the relevant PUB’s PGSR register to detect when the PUB Initialization is complete.
  7. Change back the DFIUPD0.dis_auto_ctrlupd and DBG1.dis_hif values and/or restart sending software controller updates, if they were disabled as described in step 2.
  8. Set DFIMISC.dfi_init_complete_en to 1 in order to allow the UDDRC’s state machine to exit the Initialization state.

For more information, see SDRAM Initialization Sequence.